Interface circuit arrangement for transferring data from a master processor to a slave processor

• US 4,700,292 A
• Filed: 01/17/1983
• Issued: 10/13/1987
• Est. Priority Date: 01/19/1982
• Status: Expired due to Fees

• Current Assignee: Italtel Societa Italiana Telecomunicazioni SPA (Abaco Innovazione SPA)
• Original Assignee: Italtel Societa Italiana Telecomunicazioni SPA (Abaco Innovazione SPA)
• Inventors: Campanini, Giorgio
• Primary Examiner(s): Williams, Jr., Archie E.
• Assistant Examiner(s): Lee, Thomas C.
• Application Number:
  US06/458,252
• Time in Patent Office: 1,730 Days
• Field of Search: 364/132, 364/138, 364/187, 364/200 MS File, 364/900 MS File, 360/39, 360/40, 360/48, 360/49, 371/9, 371/49
• US Class Current: 709/211
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port

Abstract

Two identical processors of a communication system, operating in master-slave relationship, each have a mass memory, a working memory, a CPU and an interface interlinked by an internal bus, the two interfaces being interconnected by an interprocessor bus serving for the exchange of data therebetween. When the mass memory of the slave process or needs updating, data words to be transferred from the mass memory of the master processor are fed via the interprocessor bus and a buffer store of the slave processor to the working memory thereof from which they are subsequently delivered to the associated mass memory while the CPU of the master processor performs other operations. A block of data words thus transferred is preceded by a header, emitted by the master CPU, which sets a word counter in the associated interface whose progressive decrementation determines the end of the transfer operation. Outgoing words are supplemented in the master interface with redundancy bits enabling correction of possible errors upon their arrival at the slave interface.

Claims

1. In a data-handling system with two substantially identical processors mated to operate in an interchangeable master-slave relationship, each processor including a mass memory, a working memory and a CPU linked with said memories by an internal bus enabling a transfer of data words between said memories and an exchange of such data words with external units,

the combination therewith of respective interfaces in said processors communicating with each other through a bidirectional interprocessor bus, each of said interfaces comprising:

input/output means connected to said internal bus;

register means connected to said input/output means for storing, upon designaton of the respective processor as the master, information received via said internal bus from the CPU thereof in regard to said data words to be transferred from corresponding mass memory to the mass memory of the slave processor, said information including the number of said data words involved in the transfer and further including instructions to be sent to the interface of the other processor identifying memory locations destined to receive the transferred data words, said register means includes;

an address register loaded by the CPU of the respective processor with an initial address of the respective working memory to which a first data word in a series of such data words is to be read out from the respective mass memory, each interface further including comparison means with inputs connected to said address register and to said input/output means for delivering to circuit means an unblocking signal enabling the transfer of an incoming data word to said interprocessor bus in response to detection of a match between the contents of said address register and a

memory address concurrently emitted by the respective CPU on the internal bus of the respective processor upon designation thereof as the master, said circuit means being connected to said address register for incrementing the contents thereof in response to said unblocking signal;

said circuit means coupled to said register means to detect the stored information for extracting data words from said input/output means and for transmitting said instructions, said information, and said extracted data words to the interface of the slave processor by way of said interprocessor bus; and

a buffer store enabled, upon designation of the respective processor as the slave, to receive data words transmitted by said circuit means of the interface of the master processor and to forward the received data words via the internal bus of the slave processor to the working memory thereof for subsequent retransmission to the respective mass memory under the control of the location-identifying instructions received from the register means of the master processor and stored in the register means of the interface of the slave processor.

2. The combinations defined in claim 1 wherein said register means further includes a word counter coupled to said input/output means for receiving from the master processor a numerical value representing the number of data words in a series to be read out, said circuit means being connected to said word counter further comprising a means for decrementing said numerical value upon the transfer of each data word and being able to detect a zero content signal from said word counter to inhibit further transfers.

3. In a data-handling system with two substantially identical processors mated to operate in an interchangeable master-slave relationship, each processor including a mass memory, a working memory and a CPU linked with said memories by an internal bus enabling a transfer of data words between said memories and an exchange of such data words with external units,

the combination therewith of respective interfaces in said processor communicating with each other through a bidirectional interprocessor bus, each of said interfaces comprising:

input/output means connected to said internal bus;

register means connected to said input/output means for storing, upon designation of the respective processor as the master, information received via said internal bus from the CPU thereof in regard to said data words to be transferred from the corresponding mass memory to the mass memory of the slave processor, said information including the number of said data words involved in the transfer and further including instructions to be sent to the interface of the other processor identifying memory locations destined to receive the transferred data words;

circuit means coupled to said register means to detect the stored information for extracting data words from said input/output means and for transmitting said instructions, said information, and said extracted data words to the interface of the slave processor by way of said interprocessor bus; and

a buffer store enabled, upon designation of the respective processor as the slave, to receive data words transmitted by said circuit means of the interface of the master processor and to forward the received data words via the internal bus of the slave processor to the working memory thereof for subsequent retransmission to the respective mass memory under the control of the location-identifying instructions received from the register means of the master processor and stored in the register means of the interface of the slave processor;

said register means further includes an address register coupled to said input/output means for receiving an initial address of the respective working memory forming contents of said address register to which a first data word in a series of such data words is to be read out from the respective mass memory, a word counter coupled to said input/output means for receiving from the master processor a numerical value representing the number of said data words in a series to be read out, said circuit means being connected to said word counter further comprising a means for decrementing said numerical value upon the transfer of each data word and being able to detect a zero content signal from said word counter to inhibit further transfer;

each interface further including comparison means with inputs connected to said address register and to said input/output means said comparison means generated enabling signal to said circuit means, enabling the transfer of an incoming data word to said interprocessor bus in response to detection of a match between said contents of said address register and a memory address concurrently emitted by the respective CPU on the internal bus of the respective processor upon designation thereof as the master, said circuit means being connected to said address register for incrementing the contents thereof in response to said enabling signal; and

said circuit means comprises a preprogrammed first sequencer coupled to said buffer store coupled to a first read-only memory means, coupled to said word counter, and coupled to said register means controlling said first read-only memory for exchanging, in response to an operating instruction from the CPU of the respective processor, preliminary signals with the interface of the other processor and a preprogrammed second sequencer coupled to a second read-only memory, coupled to said address register coupled to said internal bus and coupled to said first read only memory means controlling said second read-only memory for commanding the transfer of said data words to said other processor upon reception of a readiness signal therefrom.

4. The combination defined in claim 3 wherein each interface further comprises enabling means including an additional read-only memory, said enabling means activates said first sequencer in response to an initial instruction from the respective CPU.

5. The combination defined in claim 4 wherein said enabling means further includes decoding means said decoding means being coupled to said first read-only memory means and coupled to said input/output means for addressing said additional read-only memory in response to said initial instruction and said location-identifying instructions, said register means further including a command register with an input connected to said additional read-only memory.

6. The combination defined in claim 4 wherein each interface further includes a status register, contents of said status register are updated by at least one of said read-only memories and said status register is coupled to said respective CPU via said input/output means wherein said contents of said status register contain status of a data transfer operation, and said CPU determines said status by reading said status register.

7. The combination defined in claim 6 wherein each interface further includes an interruption-request generator responsive to signals arriving via said interprocessor bus and to commands from said first read-only memory for notifying the associated CPU of events calling for an inspection of said status register.

8. The combination defined in claim 7 wherein said circuit means further includes monitoring means coupled to said first sequencer and said status register, for detecting abnormality signals from other interface elements for establishing an alarm condition in said status register and for triggering said said first sequencer into emission by said first read-only memory of a signal activating said interuption-request generator.

9. The combination defined in claim 8 wherein said circuit means further includes timing means coupled to said monitoring means for detecting operational signals from the associated internal bus for reporting an abnormality condition to said monitoring means upon detection of an excessive duration in performing any step in a data-transfer operation.

10. The combination defined in claim 3 wherein each interface further comprises an outgoing-word register with an output connected to said interprocessor bus and an incoming-word register with an input connected to said interprocessor bus, said outgoing-word register being connected to said input/output means by way of an outgoing signal path including a correction-code generator for supplementing an outgoing word with redundancy bits, said incoming-word register being connected to said input/output means by way of an incoming signal path including said buffer store in cascade with a code corrector upon detection of said redundancy bits.

11. The combination defined in claim 10 wherein said code corrector lies upstream of said buffer store in said incoming signal path and is provided with an output line bypassing said buffer store, said output line including a normally closed electronic gate coupled to said internal bus, controlled by signals from the respective CPU to pass instruction words arriving from the other processor via said interprocessor bus when said respective CPU responds to said interruption-request generator.

12. The combination defined in claim 11 wherein each interface further includes decoding means connected to said code corrector and to said circuit means for comparing an incoming instruction word with a reference word emitted by said first read-only memory under the control of said first sequencer.

13. The combination defined in claim 10 wherein said outgoing signal path further includes an output register upstream of said correction-code generator said output register receives data from said second read-only memory under the control of said second sequencer.

14. In a data-handling system with first and second processors which are substantially identical with said first processor operated in a master function referred to as a master processor, said second processor operated in a slave function referred to as a slave processor, said second processor being an active standby ready to replace said first processor as said master processor upon cessation of operation of said first processor, whereupon said first processor becomes said slave processor, each processor including a mass memory, a working memory each of said memories contain data words and a CPU linked with said memories by an internal bus enabling a transfer of such data words between said memories and an exchange of such data words with external units,

the combination therewith of a first interface of said master processor and herein referred to as said master interface and a second interface of said slave processor, herein referred to as said slave interface, communicating with each other through a bidirectional interprocessor bus, each of said interfaces comprising:

input/output means connected to said internal bus;

register means connected to said input/output means for storing, when said register means is corresponding to said master processor, information received via said internal bus from said CPU of said master processor thereof in regard to said data words to be transferred from the respective mass memory of said master process to the mass memory of said slave processor, said information including the number of said data words involved in the transfer and further including instructions to be sent to the interface of the other processor for identifying memory locations destined to receive the transferred data words;

circuit means coupled to said register means to detect the stored information for extracting data words from said input/output means and for transmitting said instructions, said information and the extracted data words to the interface of the slave processor by way of said interprocessor bus;

a buffer store enabled, when said buffer is corresponding to said slave processor, to receive data words transmitted by said circuit means of the interface of said master processor and to forward the received data words via the internal bus of the slave processor to the working memory thereof for subsequent retransmission to the respective mass memory under the control of the location-identifying instructions received from the register means of the master processor and stored in the register means of the interface of the slave processor;

said registered means includes an address register coupled to said input/output means for receiving an initial address of the associated working memory contents of said address register to which a first data word in a series of such data words is to be read out from the respective mass memory;

said register means further includes a word counter coupled to said input/output means for receiving from said master processor a numerical value representing number of said data words in a series to be read out, said circuit means being connected to said word counter further comprising a means for decrementing said numerical value upon the transfer of each data word and being able to detect a zero-content signal from said word counter to inhibit further transfers;

said circuit means comprises a preprogrammed first sequencer coupled to said buffer store, coupled to a first read only memory means, coupled to said word counter, and coupled to said register means, controlling said first read-only memory for exchanging, in response to an operating instruction from the CPU of the respective processor, preliminary signals with the interface of the other processor and a preprogrammed second sequencer coupled to a second read-only memory, coupled to said address register, coupled to said internal bus, and coupled to said first read only memory means, controlling said second read-only memory for commanding transferring said data words to said other processor upon reception of a readiness signal therefrom, comparison means with inputs connected to said address register and to said input/output means said comparison means generates an enabling signal to said circuit means enabling the transfer of an incoming data word to said interprocessor bus in response to detection of a match between said contents of said address register and a memory address concurrently emitted by the respective CPU on the internal bus of the respective processor upon designation thereof as the master, said circuit means being connected to said address register for incrementing the contents thereof in response to said enabling signal;

enabling means including an additional read-only memory, said enabling means activates said first sequencer in response to an initial instruction from the respective CPU;

status register, whereby contents of said status register are updated by at least one of said read-only memories, said status register being coupled to said associated CPU via said input/output means, wherein contents of status register contain status of a data transfer operation and said CPU determines said status by reading said status register;

an interruption-request generator responsive to signals arriving via said interprocessor bus and to commands from said first read-only memory for notifying the respective CPU of events calling for an inspection of said status register; and

said circuit means further includes monitoring means coupled to said first sequencer, and to said status register for detecting abnormality signals from other interface elements for establishing an alarm condition in said status register and for triggering said first sequencer into emission by said first read-only memory of a signal activating said interruption-request generator.

15. The combination defined in claim 14 wherein said enabling means further includes decoding means, said decoding means coupled to said first read-only memory means and coupled to said input/output means for addressing said additional read-only memory in response to said initial instruction and said location-identifying instructions, said register means further including a command register with an input connected to said additional read-only memory.

16. The combination defined in claim 14 wherein said circuit means further includes timing means coupled to said monitoring means for detecting operational signals from the respective internal bus for reporting an abnormality condition to said monitoring means upon detection of an excessive duration in performing any step in a data-transfer operation.

17. The combination defined in claim 14 wherein each interface further comprises an outgoing-word register with an output connected to said interprocessor bus and an incoming-word register with an input connected to said interprocessor bus, said outgoing-word register being connected to said input/output means by way of an outgoing signal path including a correction-code generator for supplementing an outgoing word with redundancy bits, said incoming-word register being connected to said input/output means by way of an incoming signal path including said buffer store in cascade with a code corrector upon detection of said redundancy bits.

18. The combination defined in claim 17 wherein said code corrector lies upstream of said buffer store in said incoming signal path and is provided with an output line bypassing said buffer store, said output line including a normally closed electronic gate coupled to said internal bus controlled by signals from the respective CPU to pass instruction words arriving from the other processor via said interprocessor bus, when said respective CPU responds to said interruption-request generator.

19. The combination defined in claim 17 wherein said outgoing signal path further includes an output register upstream of said correction-code generator said output register receives data from said second read-only memory under the control of said second sequencer.

20. In a data-handling system with first and second processors which are substantially identical with said first processor operated in a master function referred to as a master processor, said second processor operated in a slave function referred to as a slave processor, said second processor being an active standby ready to replace said first processor as said master processor upon cessation of operation of said first processor, whereupon said first processor becomes said slave processor, each processor including a mass memory, a working memory each of said memories contain data words and a CPU linked with said memories by an internal bus enabling a transfer of such data words between said memories and an exchange of such data words with external units,

the combination therewith of a first interface of said master processor and herein referred to as said master interface and a second interface of said slave processor, herein referred to as said slave interface, communicating with each other through a bidirectional interprocessor bus, each of said interfaces comprising:

input/output means connected to said internal bus;

register means connected to said input/output means for storing, when said register means is corresponding to said master processor, information received via said internal bus from said CPU of said master processor thereof in regard to said data words to be transferred from respective mass memory of said master process to the mass memory of said slave processor, said information including the number of said data words involved in the transfer and further including instructions to be sent to the interface of the other processor for indentifying memory locations destined to receive the transferred data words;

circuit means coupled to said register means to detect the stored information for extracting data words from said input/output means and for transmitting said instructions, said information and the extracted data words to the interface of the slave processor by way of said interprocessor bus;

a buffer store enabled, when said buffer corresponding to said slave processor, to receive data words transmitted by said circuit means of the interface of said master processor and to forward the received data words via the internal bus of the slave processor to the working memory thereof for subsequent retransmission to the associated mass memory under the control of the location-identifying instructions received from the register means of the master processor and stored in the register means of the interface of the slave processor;

said registered means includes an address register coupled to said input/output means for receiving an initial address of the associated working memory contents of said address register to which a first data word in a series of such data words is to be read out from respective mass memory;

said register means further includes a word counter coupled to said input/output means for receiving from said master processor a numerical value representing number of said data words in a series to be read out, said circuit means being connected to said word counter further comprising a means for decrementing said numerical value upon the transfer of each data word and being able to detect a zero-content signal from said word counter to inhibit further transfers;

said circuit means comprises a preprogrammed first sequencer coupled to said buffer store, coupled to a first read only memory means, coupled to said word counter, and coupled to said register means, controlling said first read-only memory for exchanging, in response to an operating instruction from the CPU of the respective processor, preliminary signals with the interface of the other processor and a preprogrammed second sequencer coupled to a second read-only memory, coupled to said address register, coupled to said internal bus, and coupled to said first read only memory means, controlling said second read-only memory for commanding transferring said data words to said other processor upon reception of a readiness signal therefrom, comparison means with inputs connected to said address register and to said input/output means said comparison means generates an enabling signal to said circuit means enabling the transfer of an incoming data word to said interprocessor bus in response to detection of a match between said contents of said address register and a memory address concurrently emitted by respective CPU on the internal bus of the respective processor upon designation thereof as the master, said circuit means being connected to said address register for incrementing the contents thereof in response to said enabling signal;

enabling means including an additional read-only memory, said enabling means activates said first sequencer in resposne to an initial instruction from the respective CPU;

status register, whereby contents of said status register are updated by at least one of said read-only memories, said status register being coupled to said associated CPU via said input/output means, wherein contents of status register contain status of a data transfer operation and said CPU determines said status by reading said status register;

an interruption-request generator responsive to signals arriving via said interprocessor bus and to commands from said first read-only memory for notifying the respective CPU of events calling for an inspection of said status register; and

said circuit means further includes monitoring means coupled to said first sequencer, and to said status register for detecting abnormality signals from other interface elements for establishing an alarm condition in said status register and for triggering said first sequencer into emission by said first read-only memory of a signal activating said interruption-request generator, and timing means coupled to said monitoring means for detecting operational signals from the respective internal bus for reporting an abnormality condition to said monitoring means upon detection of an excessive duration in performing any step in a data-transfer operation.