×

Interface circuit arrangement for transferring data from a master processor to a slave processor

  • US 4,700,292 A
  • Filed: 01/17/1983
  • Issued: 10/13/1987
  • Est. Priority Date: 01/19/1982
  • Status: Expired due to Fees
First Claim
Patent Images

1. In a data-handling system with two substantially identical processors mated to operate in an interchangeable master-slave relationship, each processor including a mass memory, a working memory and a CPU linked with said memories by an internal bus enabling a transfer of data words between said memories and an exchange of such data words with external units,the combination therewith of respective interfaces in said processors communicating with each other through a bidirectional interprocessor bus, each of said interfaces comprising:

  • input/output means connected to said internal bus;

    register means connected to said input/output means for storing, upon designaton of the respective processor as the master, information received via said internal bus from the CPU thereof in regard to said data words to be transferred from corresponding mass memory to the mass memory of the slave processor, said information including the number of said data words involved in the transfer and further including instructions to be sent to the interface of the other processor identifying memory locations destined to receive the transferred data words, said register means includes;

    an address register loaded by the CPU of the respective processor with an initial address of the respective working memory to which a first data word in a series of such data words is to be read out from the respective mass memory, each interface further including comparison means with inputs connected to said address register and to said input/output means for delivering to circuit means an unblocking signal enabling the transfer of an incoming data word to said interprocessor bus in response to detection of a match between the contents of said address register and amemory address concurrently emitted by the respective CPU on the internal bus of the respective processor upon designation thereof as the master, said circuit means being connected to said address register for incrementing the contents thereof in response to said unblocking signal;

    said circuit means coupled to said register means to detect the stored information for extracting data words from said input/output means and for transmitting said instructions, said information, and said extracted data words to the interface of the slave processor by way of said interprocessor bus; and

    a buffer store enabled, upon designation of the respective processor as the slave, to receive data words transmitted by said circuit means of the interface of the master processor and to forward the received data words via the internal bus of the slave processor to the working memory thereof for subsequent retransmission to the respective mass memory under the control of the location-identifying instructions received from the register means of the master processor and stored in the register means of the interface of the slave processor.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×