Firmware transitional programmable sequential logic controller

• US 4,700,326 A
• Filed: 06/04/1984
• Issued: 10/13/1987
• Est. Priority Date: 06/04/1984
• Status: Expired due to Fees

• Current Assignee: Fabricom (Government of France)
• Original Assignee: Fabricom (Government of France)
• Inventors: Florine, Jean
• Primary Examiner(s): Williams, Jr., Archie E.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/616,588
• Time in Patent Office: 1,226 Days
• Field of Search: 364/900 MS File, 364/140, 364/141, 364/200 MS File
• US Class Current: 700/23
• CPC Class Codes: G05B 19/045 using logic state machines, consisting only of a memory or a programmable logic device containing the logic for the controlled machine and in which the state of its outputs is dependent on the state of its inputs or part of its own output states, e.g. binary decision controllers, finite state controllers

Abstract

An apparatus for controlling external devices in a controlled installation following a control sequence includes a scanning pulse generator arranged to generate scanning pulses at regularly offset times, and an input detection circuit comprising transition detectors each of which detectors is adapted to accept a distinct input variable signal associated with an external device or system component and a respective one of said scanning pulses to detect a transition or change of state of the input variable signal. An address signal is produced substantially immediately for accessing a sequential memory in response to the presence of a respective one of said scanning pulses and an input transition. The sequential memory stores data identifying the stages in the control sequence wherein the different storage locations are designated by a respective address defined by the particular input channel and a given stage. The sequential memory is arranged to accept the address signals from the transition detectors at the time an input transition occurs to provide the new stage data in response to each such transition and corresponding address signal. An output function memory stores the command signals for the external devices under control of the apparatus and responds to the new stage data from the sequential memory and level or alarm signals from the controlled installation to provide the associated command signal.

Claims

1. A transitional programmable sequential logic controller for the sequential control of a number of operation variables associated with external devices in a controlled installation and following a control sequence having a number of successive stages wherein each stage uniquely defines a known combination of operational variables associated with the external devices in the controlled installation wherein the next possible stages from a given stage in the control sequence are mutually exclusive and the actual next stage is determined by the current stage and a transition signal associated with at least one of the external devices and system components comprising the controlled installation, said controller comprising:

scanning pulse generator means arranged to generate N scanning pulses at regularly offset times;

input detection circuit means comprising N input signal transition detector means, each of said transition detector means being adapted to accept a distinct input variable signal associated with one of an external device and system component as well as a respective one of said scanning pulses to detect a transition in said input variable signal occurring substantially simultaneously with a respective one of said N scanning pulses;

means for producing a stage address signal corresponding to the detection of a transition in an input variable signal when at least one input transition occurs during the scanning cycle, said stage address signal being generated immediately upon the occurrence and detection of a transition associated with an input signal;

sequential memory means having a number of storage locations for storing data identifying each of the stages in the control sequence, each of the different storage locations being identified and addressable by a respective address defined by at least one input variable signal transition, said sequential memory means being adapted to accept said address signals from the N transition detectors and for providing identification data representative of a new stage in response to each address signal, and output function memory means for storing output function data defining the commands for the external devices under control, said output function memory means coupled to the sequential memory means and being adapted to accept the next stage identification data from the sequential memory means and for providing a corresponding set of command signals to control the operation of the corresponding external devices.

2. A transitional logic controller according to claim 1, wherein the scanning pulse generator means comprises a binary counter driven by clock signals to produce successive data signals each of which signals identifies a corresponding input variable signal;

multiplexer means for converting the data signals from said binary counter into successive pulses for the transition detectors, and said input detection circuit means further comprising stage change command gate means for responding to the signals from said transition detectors and for accepting the data signals from said binary counter to produce a corresponding address signal for the sequential memory means.

3. A transitional logic controller according to claim 2, wherein the transition detectors are subdivided into several groups in parallel arrangement, each of said groups being connected sequentially one at a time through selector means to sense sequentially each of said input variable signals for the occurrence of a transition in any of said input signals.

4. A transitional logic controller according to claim 1, wherein said transition detector comprises a two-bit shift register having a first input connected to an associated input channel, a second input connected to accept a respective scanning pulse associated with the input channel and a third input connected to accept an external binary level signal to inhibit the detection of a transition of an input signal associated with a said channel, and a logic gate connected to said shift register for logically combining the outputs of the shift register and the associated channel scanning pulse to activate said stage change command gate means upon the detection of an input signal transition.

5. A transitional controller according to claim 2, further comprising timing interval memory means for storing a plurality of a number of counts, each of said plurality corresponding to the timing interval data associated with and corresponding to the occurrence of a transition in an input channel signal comprising each stage in the control sequence, said timing interval memory means being addressed by the output data from the sequential memory means to access the corresponding timing interval data associated with an input channel;

timing interval control circuit means comprising generator means for producing a number of timing clock signals;

stage change detector means for producing a stage change input transition signal corresponding to the occurrence of a change of stage to load said generator means with a value of said number of timing clock signals, and counting means for counting a predetermined number of timing clock signals in response to said stage change input transition signal and the timing interval data accessed from the timing interval memory means for producing an end-of-timing interval signal to drive the controller into a new stage identified by an associated stage address in the sequential memory means.

6. A transitional logic controller according to claim 1, wherein the output function memory means includes means for accepting signals directly from the external devices and for modifying an output command signal with other output command signals stored in the output function memory means to control the external devices in accordance with a predetermined control sequence stored in the output function memory means.