Totally self-aligned CMOS process

• US 4,701,423 A
• Filed: 12/20/1985
• Issued: 10/20/1987
• Est. Priority Date: 12/20/1985
• Status: Expired due to Term

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: NCR Corporation
• Inventors: Szluk, Nicholas J.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US06/811,187
• Time in Patent Office: 669 Days
• Field of Search: 148/1.5, 29/571, 29/576 B
• US Class Current: 438/231
• CPC Class Codes: H01L 21/28525 the conductive layers comprising semiconducting material H01L21/28518, H01L21/28537 take precedence
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

Abstract

A CMOS process incorporates self-aligned buried contacts, lightly doped source/drain structures, and sidewall oxide spacers. The process is tailored so that individual process steps and structural features serve several functions, thereby providing the desirable structural features and small geometry in conjunction with fast operational speeds, reduced Miller capacitance and short channel effects in a process of minimum complexity.

Claims

1. In a process for forming a complementary metal oxide semiconductor integrated circuit, the sequence for forming self-aligned contacts and lightly doped drain structures, which comprises:

(A) forming a gate oxide layer over n-channel and p-channel active regions of a substrate having combined contact cuts and source and drain implant cuts therethrough to the substrate;

(B) forming a layer of intrinsic silicon on the resulting structure;

(C) in the presence of a masking layer, selectively subjecting the n-channel active area to a relatively high dose n-type implant to dope the associated n-channel regions of the silicon layer, silicon-to-substrate contacts and n⁺ source and drain regions;

(D) heating the structure in the presence of a masking layer and in an oxidizing atmosphere to selectively form an oxide implant masking layer over the n-channel active areas and simultaneously drive-in the n+ source and drain implants;

(E) in the presence of the oxide implant masking layer, selectively subjecting the PMOS active area to a p+- type implant to dope the associated p-channel regions of the silicon layer, silicon-to-substrate contacts, and p+ source and drain regions;

(F) removing the n-channel oxide masking layer;

(G) forming a conductor defining mask over the resulting structure and patterning the silicon layer into an array selected from the group consisting of interconnects, contacts and gate electrodes;

(H) heating the structure in an oxidizing ambient to selectively form gate electrode side wall spacers and simultaneously drive-in the source and drain regions and define the silicon-to-source and drain contacts;

(I) selectively and alternately forming relatively lightly doped p and n LDD structures in the n-channel and p-channel regions self-aligned with the respective p+ and n+ source, drain and gate regions, respectively; and

(J) selectively depositing a metal shunt layer on the patterned silcon array.

2. The complementary metal oxide semiconductor process of claim 1, wherein the oxide implant masking layer is formed selectively as defined in said oxidizing heating step (D) as the result of a patterned layer of nitride being formed over the silicon before step (D) by:

forming a nitride layer over the silicon;

forming a mask over the nitride having openings exposing the n-channel regions; and

etching the nitride in the presence of the mask to remove the nitride from the n-channel regions and thereby define the nitride into an oxidation mask.

3. The complementary metal oxide semiconductor process of claim 1, further comprising:

in implementing the silicon patterning step (G), the sequence of;

forming a nitride etch stop layer of oxide on the silicon;

forming a nitride layer on the etch stop layer;

forming a masking layer over the nitride to delineate the desired silicon pattern; and

sequentially etching the nitride, oxide and silicon to form the desired silicon pattern;

wherein during the oxidizing heating step (H), the nitride layer is used as an oxidation mask to prevent oxidation of the upper silicon surface and thereby selectively oxidize the sidewalls of the silicon to define gate electrode sidewall oxide spacers;

wherein the nitride masking layer is removed by etching after the LDD formation step (I) prior to the metal shunt formation step (J); and

wherein during said nitride etch, said nitride etch stop layer of oxide protects the underlying silicon conductor pattern.

4. In a process for forming a complementary metal oxide semiconductor integrated circuit, the sequence for forming self-aligned contacts and lightly doped drain structures which comprises:

(A) forming a gate oxide layer over the n-channel and p-channel active regions of a substrate having combined contact cuts and source and drain implant cuts therethrough to the substrate;

(B) forming a layer of intrinsic silicon on the resulting structure;

(C) forming a layer of nitride over the silicon;

(D) forming a photoresist mask over the nitride covering the p-channel regions and selectively exposing the n-channel regions;

(E) etching the nitride in the presence of the photoresist mask to expose the n-channel regions and thereby define the nitride into an oxidation mask;

(F) in the presence of the photoresist mask, subjecting the structure to an n-type implant to selectively dope the n-channel regions of the silicon layer, silicon-to-substrate contacts and n⁺ source and drain regions;

(G) removing the photoresist mask and, in the presence of the nitride oxidation mask, heating the structure in an oxidizing atmosphere to selectively form an oxide implant masking layer over the exposed n-channel active regions and simultaneously partially drive-in the n⁺ source and drain implanted regions;

(H) in the presence of the oxide implant masking layer, selectively subjecting the p-channel active areas to a p-type implant to dope the p-channel regions of the silicon layer, poly-to-substrate contacts, and p⁺ source and drain regions;

(I) removing the oxide implant masking layer;

(J) patterning the silicon layer into an array selected from the group consisting of conductors, contacts and gate electrodes;

(K) heating the structure in an oxidizing ambient to selectively form gate electrode sidewall oxide spacers and simultaneously drive-in the source and drain regions and define the silicon-to-source and drain contacts;

(L) selectively and alternately forming relatively lightly doped p-type and n-type LDD structures in the n-channel and p-channel regions self-aligned with the respective p⁺ and n⁺ source, drain and gate regions, respectively; and

(M) selectively depositing metal shunt layer on the patterned silicon array.

5. In a process for forming a complementary metal oxide semiconductor integrated circuit, the sequence for forming self-aligned contacts and lightly doped drain structures, comprising:

(A) forming a gate oxide layer over the n-channel and p-channel active regions of a substrate having combined contact cuts and source and drain implant cuts therethrough to the substrate;

(B) forming a layer of intrinsic silicon on the resulting structure;

(C) forming a layer of nitride over the silicon;

(D) forming a photoresist mask over the nitride covering the p-channel regions and selectively exposing the n-channel regions;

(E) etching the nitride in the presence of the photoresist mask to expose the n-channel regions and thereby define the nitride into an oxidation mask;

(F) in the presence of the photoresist mask, subjecting the structure to an n-type implant to selectively dope the n-channel regions of the silicon layer, silicon-to-substrate contacts and n⁺ source and drain regions;

(G) removing the photoresist mask and, in the presence of the nitride oxidation mask, heating the structure in an oxidizing atmosphere to selectively form an oxide implant masking layer over the exposed n-channel active regions and simultaneously partially drive-in the n⁺ source and drain implanted regions;

(H) in the presence of the oxide implant masking layer, selectively subjecting the p-channel active areas to a p-type implant to dope the associated p-channel regions of the silicon layer, silicon-to-substrate contacts, and p⁺ source and drain regions;

(I) removing the oxide implant masking layer;

(J) patterning the silicon layer into a selected conductor, contact and gate electrode array by;

forming an oxide etch stop layer on the silicon;

forming a nitride layer on the oxide etch stop layer;

forming a masking layer over the nitride delineating the desired silicon pattern; and

sequentially etching the nitride, oxide, and silicon to form the desired silicon pattern;

(K) using the nitride mask layer as an oxidation mask to prevent oxidation of the upper silicon surface, heating the structure in an oxidizing ambient to selectively form gate oxide sidewall spacers and simultaneously drive-in the source and drain regions and define the silicon-to-substrate contacts;

(L) selectively and alternately forming relatively lightly doped p-type and n-type LDD structures in the n-channel and p-channel regions self-aligned with the respective p⁺ and n⁺ source, drain and gate regions, respectively;

(M) removing the nitride masking layer; and

(N) selectively depositing a metal shunt layer on the patterned silicon array.