Hermetic sealing of silicon

• US 4,701,424 A
• Filed: 10/30/1986
• Issued: 10/20/1987
• Est. Priority Date: 10/30/1986
• Status: Expired due to Fees

• Current Assignee: Ford Motor Company
• Original Assignee: Ford Motor Company
• Inventors: Mikkor, Mati
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/924,712
• Time in Patent Office: 355 Days
• Field of Search: 29/588, 29/25.41, 29/577 C, 29/591, 148/DIG. 135, 148/DIG. 12, 357/74, 357/25, 357/26, 228/153, 228/165, 228/171, 228/179, 156/272.2, 156/304.2, 156/308.2, 156/309.6, 156/329, 156/556, 156/629
• US Class Current: 438/455
• CPC Class Codes: H01L 2224/05547 comprising a core and a coating
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: Y10S 148/012 Bonding, e.g. electrostatic for strain gauges
• CPC Class Codes: Y10T 29/43 Electric condenser making

Abstract

A method of forming a hermetic seal between two silicon wafers includes forming opposing troughs in each of the two wafers. In each trough are formed an isolation layer, a diffusion barrier and a tub of polysilicon. A gold strip is put on one polysilicon tub and the two silicon wafers are brought together and heated in a thermal gradient oven. A silicon gold eutectic is formed which migrates to the diffusion barrier of the silicon wafer.

Claims

1. A method of forming a hermetic seal between a first silicon wafer and a second silicon wafer including the steps of:

forming opposing troughs in each of said two silicon wafers;

forming an isolation layer suitable for forming a barrier between silicon and metal during heating;

forming a diffusion barrier suitable for limiting diffusion of gold;

forming a tub of polysilicon in the cavity lined by the diffusion barrier;

forming a gold strip on one of the polysilicon tubs;

positioning the two silicon wafers adjacent each other so that the gold strip on one polysilicon tub aligns with the polysilicon tub of the other wafer; and

heating the adjacent silicon wafers in a thermal gradient so as to form a silicon gold eutectic which migrates to the diffusion barrier of the silicon wafer which do not have gold film on the polysilicon tub.

2. A method as recited in claim 1 wherein the step of forming an isolation layer includes the step of forming a silicon dioxide layer.

3. A method as recited in claim 2 wherein the step of forming a metal diffusion barrier for gold includes forming a titanium/tungsten alloy film having a ratio of about 10:

90 wt % and having a thickness of about 0.1 microns.

4. A method as recited in claim 3 wherein the gold strip is formed narrower than the trough and has a thickness of about 2∝

4 microns.

5. A method as recited in claim 4 wherein the thermal gradient is perpendicular to the two silicon wafers and is about 100-200°

C. per centimeter.

6. A method as recited in claim 5 wherein typical dimensions of the trough are 10-200 microns wide and about 2-20 microns deep and the isolation layer grown in the troughs is a thermal oxide layer having a typical thickness of about 0.5 to 1.0 microns.

7. A method of joining two silicon wafers including the step of migrating a gold silicon eutectic across the interface between the two wafers to form a bond.

8. A method as recited in claim 7 including the further step of using a gold diffusion barrier to stop gold atoms from migrating into portions of the silicon wafer on the other side of the gold diffusion barrier.

9. A method as recited in claim 8 further comprising the use of a silicon dioxide layer between the silicon wafer and the gold diffusion barrier to provide adhesion to the metal diffusion barrier and preventing the formation of metal silicides in case of high temperature processing or usage.

10. A method as recited in claim 9 further comprising forming an electronic circuitry region within a region bounded by a seal formed by migrating a gold silicon eutectic.

11. A method as recited in claim 10 further comprising the step of forming highly doped p+paths in an n-type silicon wafer to make contact to the electronic circuitry within the hermetic seal thereby providing electrical contact without any interference with the hermetic seal.