High temperature pressure sensor with low parasitic capacitance
First Claim
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1. A silicon variable capacitance pressure sensor including:
- a first lightly doped n (or p)-type silicon wafer having a first cavity with a first p+ (or n+) doped capacitor plate with a highly doped first p+ (or n+) semiconductor path through said first wafer contacting said first capacitance plate;
a second lightly doped n (or p)-type silicon wafer having a second p+ doped (or r+) capacitor plate with a highly doped second p+ (or n+) semiconductor path through said second wafer contacting said second capacitor plate;
an insulating layer attached to said first and second silicon wafers at a region outside the extent of said first cavity preventing electrically conductive coupling between said first and second wafers, thereby reducing parasitic capacitance between the first and semiconductor paths;
said first and second capacitor plates being highly doped semiconductor regions positioned adjacent each other and separated from each other by the depth of said cavity;
said insulating layer being formed of silicon dioxide thereby producing a structure suitable for operation at relatively high temperature; and
said first and second silicon wafers being adapted for having formed therein an integrated circuit.
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Abstract
A silicon variable capacitance pressure sensor has two silicon wafers. The first wafer has a first capacitor plate contacting a highly doped first semiconductor path through the first wafer. The second wafer has a second capacitor plate contacting a highly doped second semiconductor path through the second wafer. An insulating layer is attached to the first and second wafers for preventing electrically conductive coupling between the first and second wafers, thereby reducing parasitic capacitance between the first and second semiconductor paths.
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1 Claim
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1. A silicon variable capacitance pressure sensor including:
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a first lightly doped n (or p)-type silicon wafer having a first cavity with a first p+ (or n+) doped capacitor plate with a highly doped first p+ (or n+) semiconductor path through said first wafer contacting said first capacitance plate; a second lightly doped n (or p)-type silicon wafer having a second p+ doped (or r+) capacitor plate with a highly doped second p+ (or n+) semiconductor path through said second wafer contacting said second capacitor plate; an insulating layer attached to said first and second silicon wafers at a region outside the extent of said first cavity preventing electrically conductive coupling between said first and second wafers, thereby reducing parasitic capacitance between the first and semiconductor paths; said first and second capacitor plates being highly doped semiconductor regions positioned adjacent each other and separated from each other by the depth of said cavity; said insulating layer being formed of silicon dioxide thereby producing a structure suitable for operation at relatively high temperature; and said first and second silicon wafers being adapted for having formed therein an integrated circuit.
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Current AssigneeFord Motor Company
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Original AssigneeFord Motor Company
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InventorsMikkor, Mati
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Primary Examiner(s)GRIFFIN, DONALD
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Application NumberUS06/924,721Time in Patent Office355 DaysField of Search29/25.41, 73/718, 73/724, 361/283US Class Current361/283.4CPC Class CodesG01L 9/0073 using a semiconductive diap...
