Computer system capable of interruption using special protection code for write interruption region of memory device

• US 4,701,846 A
• Filed: 01/17/1986
• Issued: 10/20/1987
• Est. Priority Date: 01/19/1985
• Status: Expired due to Term

• Current Assignee: Panafacom Limited
• Original Assignee: Panafacom Limited
• Inventors: Ikeda, Kazuhiko, Kawamura, Makoto
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US06/819,787
• Time in Patent Office: 641 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/163
• CPC Class Codes: G06F 12/145 the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
• CPC Class Codes: G06F 9/468 Specific access rights for resources, e.g. using capability register
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

A computer system capable of interruption using a special protection code for a write interruption region of a main memory, including a subsidiary memory connected with a central processor unit and the main memory. The subsidiary memory delivers a translated real address code and protection codes including ordinary protection codes and the special protection code. Checking of the special protection code in the special protection code check number is carried out when the special protection code from the subsidiary memory is present and an access instruction from the central processor unit is a write instruction. Thereby, writing into a region beyond a stack region in the main memory is possible and the information of execution of the write interruption to the region beyond the stack region in the main memory is transmitted to the central processor unit.

Claims

1. A computer system comprising:

a central processor unit;

a main memory having a stack region device connected to said central processor unit;

a subsidiary memory device connected to said central processor unit and said main memory device for delivering a translated real address and protection codes including ordinary protection codes and a special protection code;

an error detection means responsive to said ordinary protection codes from said subsidiary memory device and an access instruction from said central processor unit for checking said ordinary protection codes; and

a special protection code check means responsive to said special protection code from said subsidiary memory device and an access instruction from said central processor unit for checking said special protection code;

error detection in said error detection means being carried out when said ordinary protection codes from said subsidiary memory device do not coincide with said access instruction from said central processor unit;

checking of said special protection code in said special protection code check means being carried out when said special protection code from said subsidiary memory device is present and said access instruction from said central processor unit is a write instruction, whereby writing into a region beyond said stack region in said main memory device is possible and the information of execution of the write operation to said region beyond said stack region in said main memory device is transmitted to said central processor unit.

2. A computer system comprising:

a central processor unit having a stack pointer function;

a main memory device connected to said central processor unit and having a region for program and data, a region for write interruption, and a stack region;

a subsidiary memory device connected to said central processor unit and said main memory device for delivering a translated real address and protection codes including ordinary protection codes and a special protection code for representing an overflow beyond said stack region in said main memory device;

an error detection means responsive to said ordinary protection codes from said subsidiary memory device and an access instruction from said central processor unit for checking said ordinary protection codes; and

a special protection code check means responsive to said special protection code from said subsidiary memory device and an access instruction from said central processor unit for checking said special protection code;

error detection in said error detection means being carried out when said ordinary protection codes from said subsidiary memory device do not coincide with said access instruction from said central processor unit;

checking of said special protection code in said special protection code checking means being carried out when said special protection code from said subsidiary memory device is present and said access instruction from said central processor unit is a write instruction, whereby writing into a region beyond said stack region in said main memory device is possible and the information of the execution of the write operation to said region beyond said stack region in said main memory device is transmitted to said central processor unit.