Apparatus for correcting cyclic code data stored in memory and method therefor

• US 4,701,914 A
• Filed: 09/26/1985
• Issued: 10/20/1987
• Est. Priority Date: 09/26/1984
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Matsushita, Akira
• Primary Examiner(s): Fleming, Michael R.
• Application Number:
  US06/780,605
• Time in Patent Office: 754 Days
• Field of Search: 371/13, 371/38, 371/37, 371/43, 371/44, 371/45
• US Class Current: 714/6.1
• CPC Class Codes: H03M 13/43 Majority logic or threshold decoding
• CPC Class Codes: H04N 7/0357 for error detection or correction

Abstract

According to one aspect of the present invention, an apparatus for error correction is comprised of a data storing section for storing data to be corrected, the data including a data field and an error correction field comprised of a predetermined number of bits. The apparatus also comprises a data readout section for reading out, at a first timing, the data to be corrected from the data storing section into a first line, and for reading out, at a second timing, into a second line, the error detection section for fetching the data to be corrected as read out into the first line. The apparatus further comprises means for applying a predetermined operation to the data to be corrected, thereby generating, in synchronism with the second timing, correction data corresponding to the error data. A correction section is also used for periodically fetching both the data to be corrected as read out into the second line and the correction data generated by the error detection section. The data is also subjected to a predetermined correction processing to thereby produce corrected data. Finally, a data write section is used for storing into the data storing section the corrected data as output from the correction section.

Claims

1. An apparatus for error correction, comprising:

data storing means including first and second storage areas, the first storage area storing uncorrected code data as a data packet, the data packet having a data field and an error correction field including a predetermined number of bits;

timing signal generating means for generating first and second timing signals, said second timing signal being generated a predetermined interval of time after said first timing signal;

data readout means for reading the uncorrected data from the first storage area of the data storing means in response to the first and second timing signals, the uncorrected data being successively read out in predetermined increments of bits;

switching means for switching between first and second lines, the first line for transmitting the uncorrected data read out in response to the first timing signal, and the second line for transmitting the uncorrected data read out in response to the second timing signal;

error syndrome calculating means for calculating data errors in the uncorrected data transmitted through the first line and for generating an output representing the data errors;

error detecting means for determining whether the uncorrected data includes a predetermined quantity of data errors based on the output of the error syndrome calculating means and for generating correction data representing a result of the determination;

correction means for synchronously fetching the correction data generated by the error detecting means and the uncorrected data transmitted through the second line and for correcting errors in the uncorrected data in accordance with the correction data to thereby generate corrected data; and

write means for successively writing the corrected data into the second storage area of the data storing means in said predetermined increments of bits.

2. An apparatus according to claim 1, wherein the uncorrected data represents a majority difference set cyclic code.

3. An apparatus according to claim 2, wherein the error syndrome calculating means comprises a syndrome register including a shift register for shifting a predetermined number of bits, and the error detecting means comprises a majority logic circuit which selects by a majority output bits of the syndrome register in predetermined combinations for generating said correction data in order to correct corresponding data errors in the uncorrected data.

4. An apparatus according to claim 3, further comprising corrected state detecting means for serially fetching, bit by bit, the contents of the syndrome register after the error correction has been performed by the correction means and for detecting whether the error correction was performed correctly by the correction means.

5. An apparatus for error correction, comprising:

data storing means including first, second and third storage areas, the first storage area storing uncorrected code data as a data packet, the data packet having a data field and an error correction field including a predetermined number of bits;

timing signal generating means for generating first, second, third and fourth timing signals with predetermined time delays therebetween;

data readout means for reading the uncorrected data from the first storage area of the data storing means in response to the first and second timing signals, the uncorrected data being successively read out in predetermined increments of bits;

first switching means for switching between first and second readout lines, the first readout line for transmitting the uncorrected data read out in response to the first timing signal, and the second readout line for transmitting the uncorrected data read out in response to the second timing signal;

error syndrome calculating means for calculating data errors in the uncorrected data transmitted through the first readout line and for generating an output representing the data errors;

error detecting means for determining whether the uncorrected data includes a predetermined quantity of errors based on the output of the error syndrome calculating means and for generating correction data representing a result of the determination;

correction means for synchronously fetching the correction data generated by the error detecting means and the uncorrected data transmitted through the second readout line and for correcting errors in the uncorrected data in accordance with the correction data to thereby generate corrected data;

corrected state detecting means responsive to the output of said error syndrome calculating means for detecting whether the error correction was performed by the correction means after the error correction has been performed by the correction means and for generating an output representing the result of the detection;

second switching means for switching between first and second writing lines, the first writing line for transmitting the corrected data supplied from the correction means in response to the third timing signal, and the second writing line for transmitting the output of the corrected state detecting means in response to the fourth timing signal; and

write means for successively writing into the second storage area of the data storing means in said predetermined increments of bits the corrected data supplied from the correction means through the first writing line and for writing in the third storage area of the data storing means the output of the corrected state detecting means supplied through the second writing line.

6. An apparatus according to claim 5, wherein the uncorrected data represents a majority difference set cyclic code.

7. An apparatus according to claim 6, wherein the error syndrome calculating means comprises a syndrome register including a shift register for shifting a predetermined number of bits, and the error detecting means comprises a majority logic circuit which selects by a majority output bits of the syndrome register in predetermined combinations for generating said correction data in order to correct corresponding data errors in the uncorrected data.

8. An apparatus according to claim 7, wherein the corrected state detecting means serially fetches, bit by bit, the contents of the syndrome register after the error correction has been performed by the correction means and for detecting whether the error correction was performed correctly by the correction means.

9. A method for error correction, comprising the steps of:

generating a first timing signal;

reading uncorrected code data out of a first area of a memory in response to the first timing signal, the first area of the memory storing the uncorrected data as a data packet, the data packet having a data field and an error correction field comprised of a predetermined number of bits;

performing syndrome calculation for determining data errors in the uncorrected data read out from said first area of memory;

determining whether the uncorrected data includes data errors based on the syndrome calculation and generating correction data if data errors are determined;

generating a second timing signal;

reading the uncorrected code data out of the first area of the memory in response to the second timing signal;

synchronously fetching both the correction data and the uncorrected data read out in response to the second timing signal;

performing error correction on said uncorrected data with said correction data so as to generate corrected data; and

writing the corrected data into a second area of the memory.

10. A method according to claim 9, further comprising the steps of:

generating a third timing signal;

fetching the output of the syndrome calculation in response to the third timing signal for determining whether said error correction step was performed correctly; and

writing data representing whether the error correction step was performed correctly into a third area of the memory.