Method and apparatus for performing variable length data read transactions

• US 4,703,418 A
• Filed: 06/28/1985
• Issued: 10/27/1987
• Est. Priority Date: 06/28/1985
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Company (HP Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: James, David V.
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US06/750,377
• Time in Patent Office: 851 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/32
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/32 using combination of interrupt and burst mode transfer

Abstract

A method and apparatus for performing variable length data read transactions is presented in accordance with a preferred embodiment of the present invention. An input/output (I/O) device which performs variable length data read transactions, such as one which includes a terminal, has associated with it a command linked list, located in system memory, in which a system processor or memory controller has placed command elements. For read transactions, each element typically specifies the place in system memory where data will be transferred, and the number of bytes of data to be transferred. The I/O device autonomously fetches elements on the linked list and executes them. As bytes are being transferred from the I/O device to system memory a residual byte count is kept by the I/O device. When the I/O device has completed the data transfer, it may interrupt or otherwise provide the system processor with status information as to the data transfer. Additionally, the system processor may terminate a data transfer by sending a special flush command to the I/O device. Upon receipt of the flush command, the I/O device stops the data transaction, and returns to the system processor the residual byte count. The residual byte count is used by the system processor to determine how many bytes of information were transferred to system memory.

Claims

1. A method for receiving input from a input/output device comprising:

providing a plurality of consecutive memory locations for receiving data from the input/output device;

providing to the input/output device an address of at least one of the plurality of memory locations;

providing to the input/output device a count which specifies how many memory locations are in the plurality of memory locations;

providing a command to the input/output device to terminate transfer of data to the plurality of memory locations; and

,

receiving information as to how many of the plurality of consecutive memory locations received data from the input/output device.

2. A method as in claim 1 additionally comprising the step of placing the address and the count in a linked list of data entries consisting of memory locations.

3. A method utilizing a system processor to oversee a transfer of data from a first device to a system memory, the method comprising:

sending a command instruction from the system processor to the first device, the command instruction specifying a location in the system memory where data is to be transferred, and a unit count which indicates how much data is to be transferred;

transferring data from the first device to the system memory;

sending a second command instruction from the system processor to the first device, the command instruction the first device to stop transferring data from the first device to the system memory; and

,

sending status information from the first device to the system processor, the status information indicating how much data was transferred from the first device to the system memory.

4. A method utilizing a system processor to oversee a transfer of data from a first device to a system memory, the method comprising:

sending a command instruction from the system processor to the first device, the command instruction specifying a location in the system memory where data is to be transferred, and a unit count which indicates how much is to be transferred;

buffering data within the first device;

sending a second command instruction from the system processor to the first device, the command instruction instructing the first device to transfer buffered data from the first device to the system memory; and

,

sending status information from the first device to the system processor, the status information indicating how much data was transferred from the first device to the system memory.

5. An apparatus for performing variable length data transactions from a first device to a system memory within a processor, the apparatus comprising:

buffering means to receive data from the first device;

control means, coupled to the buffering means, for specifying to the buffering means a location in the system memory where data is to be transferred and a unit count which indicates how much data is to be transferred, and for specifying to the buffering means to transfer data it has received from the first device; and

,

wherein when the control means specifies to the buffering means to transfer data it has received from the first device, the buffering means indicates to the processor how much data has been transferred from the first device to the buffering means.