System for arbitrating use of I/O bus by co-processor and higher priority I/O units in which co-processor automatically request bus access in anticipation of need

• US 4,703,420 A
• Filed: 02/28/1985
• Issued: 10/27/1987
• Est. Priority Date: 02/28/1985
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Irwin, John W.
• Primary Examiner(s): Harkcom, Gary V.
• Assistant Examiner(s): Anderson, Lawrence E.
• Application Number:
  US06/706,804
• Time in Patent Office: 971 Days
• Field of Search: 364/200 MS File, 364/ 900 MS File
• US Class Current: 710/113
• CPC Class Codes: G06F 13/20 for access to input/output bus
• CPC Class Codes: G06F 13/36 for access to common bus or bus system

Abstract

A data processing system having a main processing unit, a memory subsystem, and a co-processor selectively connectable to said memory subsystem through an Input/Output Channel Controller which includes a control means for arbitrating access to the I/O Bus among the co-processor and the other I/O devices connected to the Bus. Since the co-processor runs programs stored in the memory subsystem, there is a tendency for the co-processor to monopolize the bus with instruction fetch cycles, thereby excluding other I/O devices from access to the bus. The control means for arbitrating responds to requests on the basis of a linear priority scheme in which the co-processor has the lowest priority. Each device, except the co-processor, is permitted to keep control of the bus until it voluntarily relinquishes it. The co-processor, on the other hand, relinquishes control of the bus in response to a request for access by any higher operator. However, control is returned automatically to the co-processor in the absence of any other request, since the co-processor continually raises its access request line.

Claims

1. A data processing system comprising in combination

(a) a Central Processing Unit (CPU)

(b) a memory subsystem connected in data transferring relationship to said CPU, and

(c) an Input/Output (I/O) subsystem connected in data transferring relationship with said CPU and said memory subsystem, said I/O subsystem comprising

(1) an I/O Channel Controller (IOCC),

(2) an I/O Bus connected to said IOCC,

(3) a plurality of Input/Output (I/O) units each of which is selectively connectable in a data transferring relationship to said I/O Bus and each of which includes means for generating an access request signal when said unit requires access to said I/O bus, and

(4) a Co-Processor which is selectively connectable in a data transferring relationship to said I/O Bus, said Co-processor having,

(a) a separate clock for asynchronously clocking an instruction fetch cycle for transferring an instruction stored in said memory subsystem to said co-processor through said bus, and

(b) means for automatically requesting access to said I/O bus for said co-processor a predetermined time, measured by said separate clock, after said coprocessor relinquishes access of said bus whether or not said co-processor needs said bus, including means for developing a two level signal and means for switching from a first level to a second level at said predetermined time.

(5) said IOCC including,

(a) arbiter means for controlling access to said I/O Bus by said co-processor and I/O units in accordance with a preestablished priority plan, said arbiter means including

(i) circuit means connected to receive said two level signal and operable in repsonse to said second level to grant said Co-processor access to said I/O bus provided none of said other I/O units are requesting access to said I/O bus, said circuit means also

connected to receive said access request signals from said I/O units and operable in response to receiving one said access request signal to cause said Co-processor to immediately return said two level signal to said other level whereby said co-processor relinquishes access of said I/O bus immediately if the co-processor is not using said I/O bus or at the termination of the current instruction fetch cycle if the Co-processor is then using said bus.

2. The system recited in claim 1 in which said memory subsystem stores program instructions to be executed by said Co-Processor and said Co-Processor is selectively connected to said memory subsystem in said data transferring relationship via said I/O Bus during each said instruction fetch cycle of said Co-Processor.

3. The system recited in claim 2 in which each of said I/O units has a priority that is established by said priority plan that is higher than the priority assigned to said Co-Processor.

4. The system recited in claim 3 in which at least one of said I/O units is a Direct Memory Access device and said means for generating an access request signal is connected to said circuit means.

5. The system recited in claim 4 in which each of said other I/O units, after obtaining access to said I/O Bus, maintains its connection until said I/O unit completes it current task and relinquishes control of said Bus.

6. The system recited in claim 5 in which each of said I/O units relinquishes control of said I/O Bus in response to the request signal of that unit becoming inactive.

7. The system recited in claim 6 in which said arbiter means includes a means repsonsive to a signal from said coprocessor indicating that access of said I/O bus has been relinquished, to momentarily disable said arbiter means to enable a new arbitration operation.