Logic Synthesizer
First Claim
1. An automated logic synthesis method of designing, on a computer, a logic circuitry implementation in a desired technology from input data to said computer comprising a description of operating characteristics to be provided by said logic circuitry, said method comprising the steps of:
- generating, via said computer, a first logic circuit design in a first logic system in accordance with said description;
simplifying said first logic design via said computer;
converting, via said computer, said simplified first logic design to a second logic design in a second logic system requiring fewer different logic operators than said first logic system, said second logic system comprising a plurality of interconnected cells and performing equivalent functions;
simplifying, via said computer, said second logic design, said step of simplifying said second logic design comprising the steps of;
applying a depth reduction sequence of logic transformations for reducing the depth of said second logic design; and
subsequently applying a size reduction sequence of logic transformations for reducing the size while possibly increasing the depth of said second logic design; and
converting, via said computer, said simplified second logic design to said desired technology.
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Abstract
Logic is synthesized from a flowchart-level description by first generating an AND/OR logic design, simplifying the AND/OR logic, converting the AND/OR logic to NAND or NOR logic, applying particular sequences of simplifying transformations to the NAND or NOR logic, converting the simplified NAND or NOR logic to a target technology, and simplifying the target technology where possible. The end result is an interconnection of primitives of the target technology in a language from which automated logic diagrams can be produced.
186 Citations
24 Claims
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1. An automated logic synthesis method of designing, on a computer, a logic circuitry implementation in a desired technology from input data to said computer comprising a description of operating characteristics to be provided by said logic circuitry, said method comprising the steps of:
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generating, via said computer, a first logic circuit design in a first logic system in accordance with said description; simplifying said first logic design via said computer; converting, via said computer, said simplified first logic design to a second logic design in a second logic system requiring fewer different logic operators than said first logic system, said second logic system comprising a plurality of interconnected cells and performing equivalent functions; simplifying, via said computer, said second logic design, said step of simplifying said second logic design comprising the steps of;
applying a depth reduction sequence of logic transformations for reducing the depth of said second logic design; and
subsequently applying a size reduction sequence of logic transformations for reducing the size while possibly increasing the depth of said second logic design; andconverting, via said computer, said simplified second logic design to said desired technology. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. An automated logic synthesis method of designing, on a computer, a logic circuitry implementation in a desired technology from input data to said computer comprising a description of operating characteristics to be provided by said logic circuitry, said method comprising the steps of:
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generating, via said computer, a first logic circuit design in a first logic system in accordance with said description; simplifying said first logic design via said computer; converting, via said computer, said first logic design to a second logic design in a second logic system requiring fewer different logic operators than in said first logic design, said second logic design comprising a plurality of interconnected cells and performing equivalent functions as said first logic design; simplifying said second logic design via said computer; converting, via said computer, said simplified second logic design to a hardware design in said desired technology comprising a plurality of interconnected hardware components; and simplifying said hardware design via said computer, said step of simplifying said hardware design comprising;
applying a first hardware transformation set for substituting technology specific components for predetermined patterns of said hardware;dotting signal lines via said computer, to decrease the number of components in said hardware logic design and to decrease fan-in in some portions of said hardware logic design even if the number of components is said portions is not decreased; adjusting path lengths in said hardware logic design via said computer; and correcting fan-out in said hardware logic design to a desired value via said computer. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22)
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23. An automated logic synthesis method of designing, on a computer, a logic circuitry implementation in a desired technology from input data to said computer comprising a description of operating characteristics to be provided by said logic circuitry, said method comprising the steps of:
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generating a first logic circuit design via said computer, in accordance with said description; simplifying said first logic design via said computer; converting, via said computer, said first logic design to a second logic design in a second logic system requiring fewer different logic operators than in said first logic design; simplifying said second logic design via said computer; converting, via said computer, said simplified second logic design to a hardware design in said desired technology comprising a plurality of interconnected hardware components and including inverters for receiving and inverting output signals from associated ones of said components; and simplifying said hardware design via said computer, said step of simplifying said hardware logic design comprising;
applying a dual-rail conversion transformation for removing some of said inverters by substituting for said some inverters an opposite phase output signal available from their associated components, said dual-rail conversion transformation being applied without regard to the effect on fan-out characteristics of said hardware logic design;
applying a first hardware transformation set for substituting technology-specific components;
dotting signal lines in said hardware logic design;
adjusting path lengths in said hardware logic design;
correcting fan-out in said hardware logic design to a desired value; and
applying said dual-rail conversion transformation only to the extent that it does not result in a fan-out exceeding said desired value.
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24. An automated logic synthesis method of designing, on a computer, a logic circuitry implementation in a desired technology from input data to said computer comprising a description of operating characteristics to be provided by said logic circuitry, said method comprising the steps of:
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generating, via said computer, a first logic circuit design accordance with said description; simplifying said first logic design via said computer; converting, via said computer, said first logic design to a second logic design in a second logic system requiring fewer different logic operators than in said first logic design; simplifying said second logic design via said computer; converting, via said computer, said simplified second logic design to a hardware design in said desired technology comprising a plurality of interconnected hardware components; and simplifying said hardware design via said computer, said step of simplifying said hardware logic design comprising selectively applying first first or second hardware transformation sets for substituting technology-specific components for predetermined patterns of said hardware components, said first hardware transformation set resulting in fewer components than said second hardware transformation set and said second hardware transformation set resulting in higher-speed logic than said first hardware transformation set.
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Specification