Wafer level integration technique

• US 4,703,436 A
• Filed: 02/01/1984
• Issued: 10/27/1987
• Est. Priority Date: 02/01/1984
• Status: Expired due to Fees

• Current Assignee: Inova Microelectronics Corporation
• Original Assignee: Inova Microelectronics Corporation
• Inventors: Varshney, Ramesh C.
• Primary Examiner(s): Krass, Errol A.
• Assistant Examiner(s): Teska, Kevin J.
• Application Number:
  US06/576,066
• Time in Patent Office: 1,364 Days
• Field of Search: 364/200, 364/900, 364/490, 365/51, 365/103, 365/104, 365/200, 365/201, 365/96, 371/10, 371/11, 29/574, 357/45
• US Class Current: 365/201
• CPC Class Codes: G01R 31/316 Testing of analog circuits G01R31/2851 takes precedence
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Wafer level integration is provided by using individually integrated circuits on a wafer substrate and generating an electrically ordered matrix of functional integrated circuits assigned from a random distribution of functional, partially functional, and non-functional circuits. Each circuit is individually tested for functionality and thereafter a conductive grid is formed on said wafer to interconnect all of the circuits on the wafer. Circuits that are tested as being non-functional are isolated prior to formation of the interconnecting grid by eliminating fuses that provide connections between the defective circuit and the conductive grid. Each matrix row includes redundant decoder lines. The redundant decoder lines are programmed to reassign functional circuits from a semiconductor wafer substrate location to a matrix row location in another matrix row having defective circuits. In this way, complete functional matrix rows are formed. Associated input and output lines are assigned in a similar manner to a correct bit position within an input and output byte.

Claims

1. A method of fabricating a group of interconnected functional circuits on a semiconductor wafer comprising:

fabricating on the semiconductor wafer a plurality of circuits each circuit having at least one associated interconnecting grid pad, each of the plurality of cirouits being electrically isolated from every other one of the plurality of circuits;

testing all of the plurality of circuits to determine whether each is a functional circuit or a non-functional circuit;

isolating each non-functional circuit from at least one of its associated interconnecting grid pads; and

after performing the step of testing, forming a conductive pattern on the semiconductor wafer to connect all of the interconnecting grid pads which pattern is independent of the distribution of functional and non-functional circuits on the wafer.

2. A method as in claim 1 wherein the plurality of circuits is arranged in rows of n circuits, each row having one row select decoder and at least one redundant row select decoder, each of the n circuits being fusably connected to each of the row select decoders and to each of the redundant row select decoders.

3. A method as in claim 2 further comprising the step of:

in a first row having r functional circuits, disconnecting each of the r functional circuits from all of the redundant row select decoders, but not from the row select decoder programmable with a first address.

4. A method as in claim 3 further comprising the steps of:

in a second row having s functional circuits, where s<

r, disconnecting each of the s functional circuits from all decoders except a redundant decoder programmable with a second address; and

in a third row having t functional circuits, where t<

r, disconnecting each of the t functional circuits from all decoders except a redundant decoder programmable with the second address, where s+t=r, to thereby provide the second address with the same number of functional circuits as the first address.

5. A method as in claim 2 wherein a set of bit position input and output lines for each bit position in a byte are connected to each one of the plurality of circuit, and the method further comprises:

assigning a pair of the input and output lines to each functional circuit in a bit position order;

isolating each functional circuit assigned a pair of input and output lines from all other bit position input and output lines.

6. A method as in claim 1 wherein the step of testing further comprises testing each of the plurality of circuits for partial functionality to identify functional portions and non-functional portions of each partially functional circuit.

7. A method as in claim 6 wherein each of the plurality of circuits includes a programmable portion decoder for addressing portions of the circuit and wherein the method further comprises:

programming each portion decoder for each partially functional circuit to address the functional portion of each such circuit when that circuit is addressed.

8. A method as in claim 1 wherein the step of isolating each non-functional circuit comprises establishing connections between each functional circuit and its associated interconnecting grid pads, but not establishing connections between each non-functional circuit and at least one of its associated interconnecting grid pads.

9. A method as in claim 1 wherein each circuit of the plurality of circuits includes a fuse connecting that circuit to an associated interconnecting grid pad, and wherein the step of isolating comprises disconnecting each non-fuctional circuit by blowing the fuse.

10. A method as in claim 1 wherein the plurality of circuits is arranged in rows, each row including a plurality of circuit select lines connected to each circuit in the row, and the method further comprises:

assigning functional circuits to a row position by isolating those functional circuits from all of the circuit select lines except that circuit select line corresponding to the row to which those functional circuits are to be assigned.

11. A method of fabricating an electrical matrix of functional memory circuits from a ransom distribution of functional and non-functional electrically isolated memory circuits formed on a semiconductor wafer, each memory circuit having associated therewith at least one interconnecting pad, the method comprising the steps of:

testing each memory circuit for functionality;

isolating each non-functional memory circuit from at least one of its interconnecting pads;

after performing the step of testing, forming a conductive pattern on the semiconductor wafer to interconnect all of the interconnecting pads which pattern is independent of the distribution of functional and non-functional circuits on the wafer;

programming circuit select decoders to assign functional memory circuits to form complete matrix rows; and

assigning input-output lines to each functional memory circuit by eliminating connections between each memory circuit and undesired input-output lines.

12. The method of claim 11 further comprising the steps of:

combining partially functional memory circuits to provide a single complete functional memory circuit assigned to a data bit line and circuit select line; and

addressing a first partial portion and a second partial portion independently by combining a partial portion address signal with a memory circuit select signal.

13. The method of claim 11 further comprising the steps of:

providing a programmable circuit select address decoder for each functional circuit;

programming each decoder to respond to a unique address, wherein each functional circuit is uniquely addressed; and

assigning input and output lines for all functional circuits to provide bit organized input and output.

14. The method of claim 11 further comprising the steps of:

providing a programmable circuit select address decoder for each functional circuit;

programming the circuit select address decoders in byte fashion, wherein each unique address addresses a byte group of functional circuits; and

assigning input and output lines within each byte group in bit position order to provide byte organized input and output.

15. The method of claim 11 further comprising the steps of:

providing a programmable circuit select address decoder for each functional circuit;

programming each circuit select address decoder to respond to a unique address, wherein each functional circuit is uniquely addressed; and

assigning common input and output lines to each functional circuit in byte fashion, whereby each functional circuit, when addressed, provides byte organized input and output.

16. A semiconductor structure comprising:

a semiconductor wafer;

a plurality of functional and non-functional circuits on the wafer each circuit having associated therewith at least one fusable connection to an associateid interconnecting pad;

a conductive pattern on the wafer to electrically connect all of the interconnecting pads which pattern is independent of the distribution of functional and non-functional circuits on the wafer; and

means for assigning an arbitrary address to each of the functional circuits, whereby non-functional circuits are isolated from the conductive pattern by disconnecting at least one of the fusable connections.

17. Apparatus as in claim 16 wherein the plurality of circuits is arranged in rows and the means for assigning comprises:

a programmable decoder for each row fusasbly connected to each circuit in the row; and

at least one redundant programmable decoder for each row also fusably connected to each circuit in the row, whereby a circuit is assigned from one row to another row by disconnecting it from all but one redundant decoder in its row and programming that redundant decoder with an address corresponding to another row.

18. Apparatus as in claim 17 further comprising:

a set of input and output leads coupled to each of the plurality of circuits; and

disconnecting means connected between each circuit and each of the input and output leads for disconnecting each circuit from all of the input and output leads except desired ones.

19. Apparatus as in claim 16 wherein the plurality of circuits is arranged in rows, further comprising:

a group of circuit select leads for each row, each of the group being coupled to each of the circuits in that row; and

fusing means connected between each circuit and each lead for assigning each circuit to a desired row, whereby a circuit is assigned to a row by disconnecting that circuit from all of the group of circuit select leads except one corresponding to the desired row.

20. A method of fabricating a group of interconnected functional circuits on a semiconductor wafer comprising:

fabricating on the semiconductor wafer a plurality of circuits arranged in rows of n circuits, each row having one row select decoder and at least one programmable redundant row select decoder, each of the n circuits being fusably connected to each of the row select decoders and to each of the programmable redundant row select decoders, each circuit having at least one associated interconnecting grid pad, and each of the plurality of circuits being electrically isolated from every other one of the plurality of circuits;

testing all of the plurality of circuits to determine whether each is a functional circuit or a non-functional circuit;

isolating each non-functional circuit from at least one of its associated interconnecting grid pads;

in a first row having r functional circuits disconnecting each of the r functional circuits from all of the redundant row select decoders, but not from the row select decoder having a first address; and

after performing the step of testing and disconnecting, forming a conductive pattern on the semiconductor wafer to connect the interconnecting grid pads which pattern is independent of the distribution of functional and non-functional circuits on the wafer.

21. A method as in claim 20 further comprising the steps of:

in a second row having s functional circuits, where s<

r, disconnecting each of the s functional circuits from all decoders except a decoder having a second address; and

in a third row having at least t functional circuits, where t<

r and s+t=r, disconnecting each of the t functional circuits from all decoders except a redundant decoder programmable with the second address, to thereby provide the second address with the same number of functional circuits as the first address.

22. A method as in claim 20 wherein a set of bit position input and output lines for each bit position in a byte are connected to each one of the plurality of circuits, and the method further comprises:

assigning a pair of the input and output lines to each functional circuit in a bit position order;

isolating each functional circuit assigned a pair of input and output lines from all other bit position input and output lines.

23. A method as in claim 20 wherein the plurality of circuits is arranged in rows, each row including a plurality of circuit select lines connected to each circuit in the row, and the method further comprises:

assigning functional circuits to a row position by isolating those functional circuits from all of the circuit select lines except that circuit select line corresponding to the row to which those functional circuits are to be assigned.

24. A method of fabricating a group of interconnected functional circuits on a semiconductor wafer comprising:

fabricating on the semiconductor wafer a plurality of electrically isolated circuits each circuit having at least one decoder means capable of being programmed to respond to specific address information, at least one function means for manipulating data connected to each of the at least one decoder means, and at least one interconnecting grid pad connected to at least one of the decoder means and the function means;

testing all of the plurality of circuits, including both the decoder means and the function means, to determine whether each circuit is a functional circuit or a non-functional circuit;

after the step of testing;

isolating each non-functional circuit from at least one of its interconnecting grid pads;

assigning arbitrary addresses to the at least one decoder means associated with the functional circuits; and

forming a common conductive grid to interconnect the interconnecting grid pads, the arrangement of which grid is independent of the distribution of functional and non-functional circuits on the wafer.

25. A method as in claim 24 wherein the step of forming a common conductive grid comprises forming a metal pattern over the circuits spearated therefrom by insulating material except where connected to the interconnecting grid pads.

26. A method as in claim 25 wherein the common conductive grid comprises a series of interconnecting lines forming an address bus and a data bus.

27. A method as in claim 26 wherein the address bus is coupled to the decoder means of each circuit and the data bus is coupled to the function means of each circuit.

28. A method as in claim 25 wherein prior to the step of forming a common conductive grid, a step is performed comprising:

programming the decoder means associated with each functional circuit with a desired address.

29. A method as in claim 28 wherein the decoder means includes a plurality of fusible connections, and the step of programming the decoder means comprises opening seleclted ones of the plurality of fusible connections.

30. A method as in claim 28 wherein the step of programming the decoder means comprises:

programming a plurality of the decoder means with the same specific address so that a plurality of the decoder means respond to the same specific address.

31. A method as in claim 28 wherein each of the decoder means is programmed with a unique specific address different from the address for each other decoder means.

32. A semiconductor structure comprising:

a semiconductor wafer;

a plurality of functional and non-functional circuits formed on the wafer, each circuit having at least one decoder means capable of being programmed to respond to specific address information, at least one function means for manipulating data, the function means being connected to each of the at least one decoder means, and at least one interconnecting grid pad connected to at least one of the decoder means and the function means;

means for assigning an arbitrary address to each of the functional circuits, whereby non-functional circuits are isolated from the conductive grid by disconnecting at least one of the interconnecting grid pads from each non-functional circuit; and

a conductive grid formed on the water to electrically connect the interconnecting grid pads, which common conductive grid is independent of the distribution of functional and non-functional circuits on the wafer, the common conductive providing a series of interconnecting conductive lines for transfer of address information and data, which conductive lines are connected to at least the function means in each of the plurality of circuits.