Wafer level integration technique
First Claim
1. A method of fabricating a group of interconnected functional circuits on a semiconductor wafer comprising:
- fabricating on the semiconductor wafer a plurality of circuits each circuit having at least one associated interconnecting grid pad, each of the plurality of cirouits being electrically isolated from every other one of the plurality of circuits;
testing all of the plurality of circuits to determine whether each is a functional circuit or a non-functional circuit;
isolating each non-functional circuit from at least one of its associated interconnecting grid pads; and
after performing the step of testing, forming a conductive pattern on the semiconductor wafer to connect all of the interconnecting grid pads which pattern is independent of the distribution of functional and non-functional circuits on the wafer.
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Accused Products
Abstract
Wafer level integration is provided by using individually integrated circuits on a wafer substrate and generating an electrically ordered matrix of functional integrated circuits assigned from a random distribution of functional, partially functional, and non-functional circuits. Each circuit is individually tested for functionality and thereafter a conductive grid is formed on said wafer to interconnect all of the circuits on the wafer. Circuits that are tested as being non-functional are isolated prior to formation of the interconnecting grid by eliminating fuses that provide connections between the defective circuit and the conductive grid. Each matrix row includes redundant decoder lines. The redundant decoder lines are programmed to reassign functional circuits from a semiconductor wafer substrate location to a matrix row location in another matrix row having defective circuits. In this way, complete functional matrix rows are formed. Associated input and output lines are assigned in a similar manner to a correct bit position within an input and output byte.
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Citations
32 Claims
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1. A method of fabricating a group of interconnected functional circuits on a semiconductor wafer comprising:
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fabricating on the semiconductor wafer a plurality of circuits each circuit having at least one associated interconnecting grid pad, each of the plurality of cirouits being electrically isolated from every other one of the plurality of circuits; testing all of the plurality of circuits to determine whether each is a functional circuit or a non-functional circuit; isolating each non-functional circuit from at least one of its associated interconnecting grid pads; and after performing the step of testing, forming a conductive pattern on the semiconductor wafer to connect all of the interconnecting grid pads which pattern is independent of the distribution of functional and non-functional circuits on the wafer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of fabricating an electrical matrix of functional memory circuits from a ransom distribution of functional and non-functional electrically isolated memory circuits formed on a semiconductor wafer, each memory circuit having associated therewith at least one interconnecting pad, the method comprising the steps of:
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testing each memory circuit for functionality; isolating each non-functional memory circuit from at least one of its interconnecting pads; after performing the step of testing, forming a conductive pattern on the semiconductor wafer to interconnect all of the interconnecting pads which pattern is independent of the distribution of functional and non-functional circuits on the wafer; programming circuit select decoders to assign functional memory circuits to form complete matrix rows; and assigning input-output lines to each functional memory circuit by eliminating connections between each memory circuit and undesired input-output lines. - View Dependent Claims (12, 13, 14, 15)
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16. A semiconductor structure comprising:
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a semiconductor wafer; a plurality of functional and non-functional circuits on the wafer each circuit having associated therewith at least one fusable connection to an associateid interconnecting pad; a conductive pattern on the wafer to electrically connect all of the interconnecting pads which pattern is independent of the distribution of functional and non-functional circuits on the wafer; and means for assigning an arbitrary address to each of the functional circuits, whereby non-functional circuits are isolated from the conductive pattern by disconnecting at least one of the fusable connections. - View Dependent Claims (17, 18, 19)
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20. A method of fabricating a group of interconnected functional circuits on a semiconductor wafer comprising:
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fabricating on the semiconductor wafer a plurality of circuits arranged in rows of n circuits, each row having one row select decoder and at least one programmable redundant row select decoder, each of the n circuits being fusably connected to each of the row select decoders and to each of the programmable redundant row select decoders, each circuit having at least one associated interconnecting grid pad, and each of the plurality of circuits being electrically isolated from every other one of the plurality of circuits; testing all of the plurality of circuits to determine whether each is a functional circuit or a non-functional circuit; isolating each non-functional circuit from at least one of its associated interconnecting grid pads; in a first row having r functional circuits disconnecting each of the r functional circuits from all of the redundant row select decoders, but not from the row select decoder having a first address; and after performing the step of testing and disconnecting, forming a conductive pattern on the semiconductor wafer to connect the interconnecting grid pads which pattern is independent of the distribution of functional and non-functional circuits on the wafer. - View Dependent Claims (21, 22, 23)
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24. A method of fabricating a group of interconnected functional circuits on a semiconductor wafer comprising:
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fabricating on the semiconductor wafer a plurality of electrically isolated circuits each circuit having at least one decoder means capable of being programmed to respond to specific address information, at least one function means for manipulating data connected to each of the at least one decoder means, and at least one interconnecting grid pad connected to at least one of the decoder means and the function means; testing all of the plurality of circuits, including both the decoder means and the function means, to determine whether each circuit is a functional circuit or a non-functional circuit; after the step of testing; isolating each non-functional circuit from at least one of its interconnecting grid pads; assigning arbitrary addresses to the at least one decoder means associated with the functional circuits; and forming a common conductive grid to interconnect the interconnecting grid pads, the arrangement of which grid is independent of the distribution of functional and non-functional circuits on the wafer. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31)
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32. A semiconductor structure comprising:
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a semiconductor wafer; a plurality of functional and non-functional circuits formed on the wafer, each circuit having at least one decoder means capable of being programmed to respond to specific address information, at least one function means for manipulating data, the function means being connected to each of the at least one decoder means, and at least one interconnecting grid pad connected to at least one of the decoder means and the function means; means for assigning an arbitrary address to each of the functional circuits, whereby non-functional circuits are isolated from the conductive grid by disconnecting at least one of the interconnecting grid pads from each non-functional circuit; and a conductive grid formed on the water to electrically connect the interconnecting grid pads, which common conductive grid is independent of the distribution of functional and non-functional circuits on the wafer, the common conductive providing a series of interconnecting conductive lines for transfer of address information and data, which conductive lines are connected to at least the function means in each of the plurality of circuits.
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Specification