Non-volatile random access memory cell
First Claim
1. A non-volatile random access memory cell comprising:
- a volatile memory cell for storing a datum comprisingflip-flop circuit having a first and second nodes on which complementary signals corresponding to the stored datum are output, anda first capacitor connected to said first node; and
a non-volatile memory cell comprisinga second capacitor, operatively connected to said second node, having a capacitance larger than that of said first capacitor,a memory transistor having a floating gate, connected between said second node and said second capacitor, said memory transistor acting as a switch in accordance with the polarity of the charge stored at said floating gate,a capacitor circuit comprising a tunnel capacitor operatively connected to said floating gate,means, operatively connected to said capacitor circuit, for applying a writing voltage having an amplitude large enough to cause a tunnel current to flow through said tunnel capacitor,a first transistor, operatively connected to said second node and to said capacitor circuit, for controlling the polarity of said tunnel current in accordance with said stored datum, said first transistor generating an output in response to one of said complementary signals at said second node, anda second transistor, operatively connected to said capacitor circuit receiving the output of said first transistor, for controlling the polarity of said tunnel current in accordance with said stored datum,said first and second transistors cooperatively controlling the polarity of the tunnel current to flow through said tunnel capacitor when said writing voltage is applied to said capacitor circuit, one of said first and second transistors being ON and the other being OFF when said tunnel current is to be flown, said polarity of the tunnel current being controlled to be in one of two directions opposite to each other depending on which one of said first and second transistors is ON, said two directions being such that said floating gate is provided with one of negative and positive charges by said tunnel current in one of said two directions, respectively.
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Accused Products
Abstract
A non-volatile random access memory (NVRAM) cell including a volatile static type random access memory cell consisting of a flop-flip circuit having two nodes on which a paired bit signal are accessed and a non-volatile electrically erasable programmable read-only memory (EEPROM) cell consisting of a memory transistor having a floating gate, a capacitor circuit, on which a voltage called as a writing voltage is applied, including a tunnel capacitor, and two transistors for determining the polarity of the charge being to be stored at the floating gate with a tunnel current in the tunnel capacitor corresponding to the level of the bit signal existing at one of the two nodes in the flip-flop circuit. When the power supply voltage of the NVRAM cell is turned off, the EEPROM cell stores the positive or negative charge at the floating gate corresponding to the bit signal level at the node in the flip-flop circuit holding the charge after the power supply voltage and the writing voltage are turned off. When the power supply voltage is turned on, the EEPROM cell recalls the state of the flip-flop circuit so as to be same as before using the charge stored at the floating gate.
54 Citations
6 Claims
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1. A non-volatile random access memory cell comprising:
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a volatile memory cell for storing a datum comprising flip-flop circuit having a first and second nodes on which complementary signals corresponding to the stored datum are output, and a first capacitor connected to said first node; and a non-volatile memory cell comprising a second capacitor, operatively connected to said second node, having a capacitance larger than that of said first capacitor, a memory transistor having a floating gate, connected between said second node and said second capacitor, said memory transistor acting as a switch in accordance with the polarity of the charge stored at said floating gate, a capacitor circuit comprising a tunnel capacitor operatively connected to said floating gate, means, operatively connected to said capacitor circuit, for applying a writing voltage having an amplitude large enough to cause a tunnel current to flow through said tunnel capacitor, a first transistor, operatively connected to said second node and to said capacitor circuit, for controlling the polarity of said tunnel current in accordance with said stored datum, said first transistor generating an output in response to one of said complementary signals at said second node, and a second transistor, operatively connected to said capacitor circuit receiving the output of said first transistor, for controlling the polarity of said tunnel current in accordance with said stored datum, said first and second transistors cooperatively controlling the polarity of the tunnel current to flow through said tunnel capacitor when said writing voltage is applied to said capacitor circuit, one of said first and second transistors being ON and the other being OFF when said tunnel current is to be flown, said polarity of the tunnel current being controlled to be in one of two directions opposite to each other depending on which one of said first and second transistors is ON, said two directions being such that said floating gate is provided with one of negative and positive charges by said tunnel current in one of said two directions, respectively. - View Dependent Claims (3, 4, 5, 6)
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2. A non-volatile random access memory cell comprising:
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a volatile memory cell for storing a datum comprising flip-flop circuit having a first and second nodes on which complementary signals corresponding to the stored datum are output, and a first capacitor connected to said first node; and a non-volatile memory cell comprising a memory transistor having a floating gate, connected to said second node, said memory transistor acting as a switch in accordance with the polarity of the charge stored at said floating gate, a capacitor circuit comprising a tunnel capacitor operatively connected to said floating gate, means, operatively connected to said capacitor circuit, for applying a writing voltage having an amplitude large enough to cause a tunnel current to flow through said tunnel capacitor, a first transistor, operatively connected to said second node and to said capacitor circuit, for controlling the polarity of said tunnel current in accordance with said stored datum, said first transistor generating an output in response to one of said complementary signals at said second node, a second transistor, operatively connected to said capacitor circuit receiving the output of said first transistor, for controlling the polarity of said tunnel current in accordance with said stored datum, and a third transistor, connected between said second node and said memory transistor, for switching the connection between said second node and said memory transistor, said first and second transistors cooperatively controlling the polarity of the tunnel current to flow through said tunnel capacitor when said writing voltage is applied to said capacitor circuit, one of said first and second transistors being ON and the other being OFF when said tunnel current is to be flown, said polarity of the tunnel current being controlled to be in one of two directions opposite to each other depending on which one of said first and second transistors is ON, said two directions being such that said floating gate is provided with one of negative and positive charges by said tunnel current in one of said two directions, respectively.
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Specification