Universal apparatus for detecting faults in microprocessor systems

• US 4,703,482 A
• Filed: 05/30/1986
• Issued: 10/27/1987
• Est. Priority Date: 02/19/1986
• Status: Expired due to Fees

• Current Assignee: Hydro-Quebec (Province of Québec)
• Original Assignee: Hydro-Quebec (Province of Québec)
• Inventors: Laflamme, Donald, Auger, Jean
• Primary Examiner(s): Atkinson, Charles E.
• Application Number:
  US06/868,444
• Time in Patent Office: 515 Days
• Field of Search: 371/16, 371/20, 324/73 R, 324/73 AT, 364/200, 364/900
• US Class Current: 714/28
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation

Abstract

A universal apparatus for the detection of faults in microprocessor systems. Microprocessors are commonly commercialized under the form of integrated circuits having a plurality of pins. The apparatus thus comprises a connector provided with pins so positioned that they can be inserted in the connection device of the microprocessor of a faulty system, in the place of the pins of this microprocessor after the same has been withdrawn. An interface defines for each pin of the connector a line having a programmable direction. A programmed controller associated with a memory which stores a copy of the software of the faulty system is connected to the interface for (a) programming the direction of the lines in order to simulate the interconnections which are normally established between the system and its microprocessor, and (b) carrying out tests on this system through the simulated interconnections for detecting the fault. The controller can of course be programmed to detect faults in a plurality of different microprocessor systems. The memory associated therewith then stores a copy of the software of all these systems.

Claims

1. An apparatus for detecting a fault in a system including a microprocessor, said microprocessor comprising a plurality of pins individually connected to the system through a connection device, said detecting apparatus comprising:

a connector provided with pins so positioned that they can be individually connected to the system through said connection device, in the place of the pins of the microprocessor after the latter has been withdrawn from the system;

an interface defining for each pin of said connector a line connected to this pin and having a programmable direction; and

control means connected to the interface for (a) programming the direction of the lines defined by said interface in order to simulate by means of these lines interconnections which are normally established between the system and its microprocessor, and (b) carrying out tests on the microprocessor system through the interconnections simulated by the interface for detecting the fault in said system.

2. An apparatus according to claim 1, in which said connector and the microprocessor comprise a same number of pins, the pins of said connector being positioned in the same manner as those of the microprocessor so that they can be individually connected to the system through said connection device.

3. The apparatus of claim 1, wherein the interface comprises a pair of buffers for each line defined by said interface, the buffers of each pair being connected in parallel and being oriented so as to conduct in opposite directions.

4. An apparatus according to claim 3, wherein each buffer comprises a control input through which a conducting or non-conducting state is given to the buffer, the direction of each line defined by the interface being programmed by the control means through said inputs of the buffers of the corresponding pair of buffers.

5. The apparatus of claim 4, in which the control input of a first buffer of each pair is an inverting control input while the control input of the second buffer of the same pair is a non-inverting control input, said inverting and non-inverting inputs of the buffers of a same pair being interconnected together to form a single control input of this pair of buffers so that the direction of the corresponding line defined by the interface can be programmed by applying a signal on said single control input of the pair of buffers.

6. An apparatus according to claim 5, in which the interface comprises programmable input/output circuits interposed between, on the one hand, the lines defined by the interface and the single control inputs of the pairs of buffers, and, on the other hand, the control means.

7. The apparatus of claim 1, wherein the control means comprises means for storing a copy of the software of the microprocessor system.

8. An apparatus according to claim 7, wherein the control means further comprises means for reading through the interface and said connector the software stored within the microprocessor system, and means for comparing the so read software with said copy in order to detect any error in the software stores within the system, reading of the software stored within the microprocessor system and comparison of the so read software with said copy constituting one of said tests carried out on the system.

9. The apparatus of claim 1, in which the control means comprises a controller programmed to carry out, through the interface and said connector, tests on a plurality of systems including microprocessors of different types, and to program the direction of the lines defined by the interface in relation with the type of the microprocessor of the system connected to said connector through said connection device.

10. An apparatus according to claim 1, in which the control means comprises a controller programmed to carry out, through said interconnections simulated by the interface, tests on a plurality of microprocessor systems of different types when connected to said apparatus through said connector.

11. The apparatus of claim 10, wherein the control means further comprises a memory for storing a copy of the software of said microprocessor systems.

12. An apparatus according to claim 10, wherein the control means comprises means for selecting the type of the microprocessor system connected to said connector in order to allow said controller to use a program portion associated with this type of microprocessor system.

13. The apparatus of claim 12, in which said selecting means comprises control push buttons and display means.

14. An apparatus according to claim 12, in which the control means further comprises means for selecting the tests to be carried out on the microprocessor system connected to said connector.

15. The apparatus of claim 14, wherein said test selecting means comprises control push buttons and display means.

16. An apparatus according to claim 1, wherein the control means comprises means for selecting the tests to be carried out on the microprocessor system.

17. The apparatus of claim 16, in which the selecting means comprises control push buttons and display means.

18. An apparatus according to claim 1, wherein the control means comprises display means for displaying the result of the tests carried out on the microprocessor system.

19. An apparatus according to claim 1, wherein said tests comprise dynamic tests, said control means comprising a controller programmed to carry out the dynamic tests which require no intervention from a user of said apparatus.

20. The apparatus of claim 1, in which said tests comprise static tests, said control means comprising a controller programmed to carry out said static tests which each allow a user of said apparatus to determine whether a part of the circuit of the system is faulty by means of at least one measurement carried out by the user on the microprocessor system with a measuring instrument.