Programmed implementation of real-time multiresolution signal processing apparatus

• US 4,703,514 A
• Filed: 09/16/1985
• Issued: 10/27/1987
• Est. Priority Date: 09/16/1985
• Status: Expired due to Term

• Current Assignee: RCA Corporation (General Electric Company)
• Original Assignee: RCA Corporation (General Electric Company)
• Inventors: van der Wal, Gooitzen S.
• Primary Examiner(s): Moore, David K.
• Assistant Examiner(s): Todd, Jacqueline
• Application Number:
  US06/776,474
• Time in Patent Office: 771 Days
• Field of Search: 382/41, 382/27, 382/49, 382/54, 382/56, 358/284
• US Class Current: 382/302
• CPC Class Codes: G06F 17/10 Complex mathematical operations function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544

Abstract

Multiresolution processing apparatus (which may be programmed as pyramid processing apparatus) comprised of a filter logic unit comprised of one or a plurality of identical interconnected programmable modules; a set of programmable multiplexers (MUX), a plurality of programmable random access-memories (RAM), and a timing and control means including an instruction memory for programming the flow of information data through and the operation of the filter logic unit, the set of MUX and the plurality of RAM. This permits a single stage to sequentially operate as each separate stage of an FSD or Burt Pyramid analyzer or of a pyramid synthesizer.

Claims

1. In a delayed real time multiresolution processing apparatus utilizing digital techniques for operating during each of successive time cycles at respective levels of resolution which respective levels of resolution differ from each other, on a series of termporal signal samples that define at least one block of an n-dimensional information component, where n is a given integer of at least one, each of said time cycles being composed of a certain number of sample periods that is at least as large as the number of temporal signal samples in said series;

the combination comprising;

a programmable filter logic unit for deriving during each successive time cycle a set of one or more sampled-signal outputs therefrom as specified selectable functions of a set of one or more sampled-signal inputs thereto in accordance with the values of applied first digital control signals, whereby said programmable filter logic unit sequentially performs processing at each of said respective levels of resolution;

a plurality of addressable read/write memory means each of which is separately addressable in each of said n dimensions, each of said memory means being controllable in accordance with the values of applied second digital control signals;

programmable coupling means including a first set of multiplexers (MUX) individually associated with each of said filter logic unit outputs and a second set of MUX individually associated with each of filter logic unit inputs for selectively coupling;

(1) any filter logic unit output as a write-input to a selected one of at least two of said memory means through that one of said first set of MUX individually associated with that filter logic unit output,

(2) the read-output of any one of said at least two of said memory means to a selected one of said filter logic unit inputs through that one of said second set of MUX individually associated with that filter logic unit input,

(3) any filter logic unit output directly to any selected one of said filter logic unit inputs through those respective ones of said first and second sets of MUX that are individually associate with that filter logic unit output an that selecte one of said filter logic unit inputs, and

(4) an applied external series of said temporal signal samples to any selected one of said filter logic unit inputs through that one of said second set of MUX individually associated with that selected one of said filter logic unit inputs,

all in accordance with the values of applied third digital control signals; and

timing and control means for deriving and applying said respective first, second and third digital control signals which together determine the level of resolution of processing done by said programmable filter logic unit during each said successive time cycle, said timing and control means including addressable instruction memory means for determining the respective values of said first, second and third digital control signals during each one of said certain number of sample periods in each of said time cycles.

2. The apparatus defined in claims 1, wherein:

said delayed real time multiresolution processing apparatus is comprised of delayed real time pyramid processing apparatus.

7. The apparatus defined in claim 1, wherein:

said addressable isntruction memory means is comprised of a programmable reads-only-memory (PROM) that stores an instruction program at predetermined addresses thereof.

8. The apparatus defined in claim 1, wherein:

said addressable instruction memory means is comprised of a random-access-memory (RAM), and means for storing an instruction program at predetermined addresses in said RAM.

3. In a delayed real time pyramid processing apparatus utilizing digital techniques for operating, during each of successive time cycles, on a series of temporal signal samples that define at least one block of an n-dimensional informaation component, where n is a given integer of at least one, each of said time cycles being composed of a certain number of sample periods that is at least as large as the number of temporal signal samples in said series;

the combination comprising;

programmable filter logic unit for deriving a set of one or more sampled-signal outputs therefrom as specified selectable functions of a set of one or more sampled-signal inputs thereto in accordance with the values of applied first digital control signals;

a plurality of addressable read/write memory means each of which is separately addressable in each of said n dimensions, each of said memory means being controllable in accordance with the values of applied second digital control signals;

programmable coupling means including a first set of multiplexers (MUX) individually associated with each of said filter logic unit outputs and a second set of MUX individually associated with each of filter logic unit inputs for selectively coupling;

(1) any filter logic unit as a write-input to a selected one of at 1east two of said memory means through that one of said first set of MUX individually associated with that filter logic unit output,

(2) the read-output of any one of said at least two of said memory means to a selected one of said filter logic unit inputs through that one of said second set of MUX individually associated with that filter logic unit input,

(3) any filter logic unit output directly to any selected one of said filter logic unit inputs through those respective ones of said first and second sets of MUX that are individually associated with that filter logic unit output and that selected one of said filter logic unit inputs and

(4) an applied external series of said temporal signal samples to any selecte one of said filter logic unit input through that one of said second set of MUX individually associate with that selecte one of said filter logic unit inputs,

all in accordance with the values of applied third digital control signals; and

timing and control means for deriving and applying said respective first, second and third digital control signals, said timing and control means including addressable instruction memory means for determining the respective values of said first, second and third digital control signals during each one of said certain number of sample period in each of time cycles--wherein;

said series of temporal signal samples define the spatial frequency spectrum of a two-dimensional image;

said filter logic unti is comprised of at least one given filter logic unit module having first and second signal inputs for sampled signals, a control input for said first digital control signals, and first and second signal outputs for sampled signals; and

said given module includes a multitap two-dimensional digital filter having a given number of hernel weighting function coefficients in each dimension which are programmable in accordance with said first digital control signals applied to said control input, a first MUX for selectively applying a sampled signal applied to said first signal input or a ZERO word as a filter input to said digital filter in accordance with said first digital control signals applied to said control input, whereby said digital filter inserts a given delay equal to the sum of delays in each of its two dimensions between its filter input and its filtered output, first programmable delay means for selectively delaying said filter input by a given amount equal to the longer of the delays in each of said filter'"'"'s two dimensions or by twice said given amount in accordance with said first digital signals applied to said control input, second delay means for inserting a delay equal to the shorter of the delays in each of said filter'"'"'s two dimesnions, a second MUX for selectively applying a sampled signal applied to said second signal input or said delay filter input as an input to said second delay means in accordance with said first digital control signals applied to said control input, an arithmetic logic unit (ALU) for selectively adding or subtracting a sampled signal applied to its second input to or from a sampled signal applied to its first input in accordance with said first digital control signals applied to said control input, means for applying the output of said second delay means as said sampled signal to said first input of said ALU, means for applying the delayed filtered output of said filter to said first signal output and also as said sampled signal to said second input of said ALU, and a third MUX for selectively applying the output of said second delay means or the sampled signal output from said ALU to said second signal output in accordance with said first digital control signals applied to said control input.

4. The apparatus defined in claim 3, wherein:

said filter logic unit is comprised of a single given filter logic unit module; and

said timing and control means provides first digital control signals to said single given module which result in (1) its first MUX always applying said sampled signal applied to its first signal input to its filter input, (2) its first delay means providing a delay equal to said given amount of delay, (3) its second MUX always applying its delayed filter input to the input of its second delay means, (4) its ALU always subtracting the sampled signal applied to the second input thereof from the sampled signal applied to the first input thereof, and (5) its third MUX always applying the output of its ALU to its second signal output;

whereby said filter logic unit operates as a filter-subtract-deimate (FSD) pyramid analyzer stage.

5. The apparatus defined in claim 3, wherein:

said filtler logic unit is comprised of first and second given filter logic unit modules, with said first and second signal inputs of said given module being respectively connected to said first and second signal outputs of said first given module;

said timing and control means provides first digital control signals to said first given module which result in (1) its first MUX always applying said sampled signal applied to its first signal input to its filter input, (2) its first delay means providing a delay equal to twice said given amount of delay, (3) its second MUX always applying its delayed filter input to the input of its second delay means, and (4) its third MUX always applying the output of its second delay means to its second signal output; and

said timing and control means provides first digital control signals to said second given module which result in (5) its first MUX alternatively applying said sampled signal applied to its first signal input and said ZERO word to its filter input, (6) its second MUX always applying said sampled signal applied to its second signal input to the input of its second delay means (7) its ALU always subtracting the sampled signal applied to the second input thereof from the sampled signal applied to the first input thereof, and (8) its third MUX always applying the output of its ALU to its second signal output;

whereby said filter logic unit operates as a Burt Pyramid analyzer stage.

6. The apparatus defined in claim 3, wherein:

said filter logic unit is comprised of a single given filter logic unit module; and

said timing and control means provides first digital control signals to sad single given module which result in (1) its first MUX alternatively applying said sampled signal applied to its first signal input and said ZERO word to its filter input, (2) its second MUX always applying the sampled signal applied to its second signal input to the input of its second delay means, (3) its ALU adding the sampled signal applied to the second input thereof to the sampled signal applied to the first input thereof, and (4) its third MUS always applying the output of its ALU to its second signal output;

whereby said filter logic unit operates as a pyramid synthesizer stage.

9. In a delayed real time pyramid processing apparatus utilizing digital techniques for operating, during each of successive time cycles, on a series of temporal signal samples that define at least one block of an n-dimesnional information component, where n is a given integer of at least one, each of said time cycles being composed of a certain number of sample periods that is at least as large as the number of temporal signal samples in said series;

the combination comprising;

a programmable filter logic unit for deriving a set of one or more sampled-signal outputs therefrom as specified selectable functions of a set of one or more sampled-signal inputs thereto in accordance with the values of applied first digital control signals;

a plurality of addressable read/write memory means each of which is separately addressable in each of said n dimesnions, each of said memory means being controllable in accordance with the values of applied second digital control signals;

programmable coupling means including a first set of multiplexers (MUX) individually associated with each of said filter logic unit outputs and a second set of MUX individually associated with each of filter logic unit inputs for selectively coupling;

(1) any filter logic unit output as a write-input ot a selected one of at least two of said memory means through that one of said first set of MUX individually associated with that filter logic unit output,

(2) the read-output of any one of said at least two of said memory means to a selected one of said filter logic units through that one of said second set of MUX individually associated with that filter logic unit input,

(3) any filter logic unit output directly to any selected one of said filter logic unit inputs through those respective ones of said first and second sets of MUX that are individually associated with that filter logic unit output and that selected one of said filter logic unit inputs, and

(4) an applied external series of said temporal signal samples to any selected one of said filter logic unit inputs through that one of said second set of MUX individually associated with that selected one of said filter logic unit inputs,

all in accordance with the values of applied third digital control signals; and

timing and control means for deriving and applying said respective first, second and third digital control signals, said timing and control means including addressable instruction memory means for determining the respective values of said first, second and third digital control signals during each one of said certain number of sample periods in each of said time cycles--wherein;

said instruction memory means includes a memory that stores an instruction program at predetermined addressed thereof and an address counter incremented by each of successive clock signals applied thereto, said address counter being coupled to said memory for addressing that instruction of said program which is stored at the address then registered in said address counter, thereby causing said memory to read out the addressed instruction from said memory; and

said timing and control means further includes instruction decode means responsive at least in part to the read out instruction from said memory for selectively generating at least one given control signal, and means responsive to said one given control signal being generated for jam loading the instruction then being read out of said memory into said address counter.

10. The apparatus defined in claim 9, wherein:

said isntruction decode means selectively generates a second given control signal in addition to sasid one given control signal, and

said timing and control means includes a cycle timer having a given count capacity which is incremented by each of successive clock signals applied thereto, said cycle timer applying a flag control input to said instruction decode means in response to registering a predetermined count for affecting the operation of said instruction decode means, and means responsive to the generation of said second given control signal for jam loading the instruction then being read out of said memory into said cycle timer.

11. The apparatus defined in claim 9, wherein:

said instruction decode means selectively generates a second given control signal in addition to said one given control signal and also generates a "clock one" signal in response to at least one predetermined instruction being read out of said memory; and

said timing and control means includes a loop counter having a given count capacity which is incremented by each "clock one" signal applied thereto from said instruction decode means, said loop counter applying a flag control input to said instruction decode means in response to registering a predetermined count for affecting the operation of said instruction decode means, and means responsive to the generation of said second given control signal for jam loading the instruction then being read out of said memory into said loop counter.

12. The apparatus defined in claim 9, wherein:

said series of temporal signal samples are derived from a television video signal comprised of successive telelvision fields each of which is comprised of a plurality of horizontal scan lines;

means for applying a V_B video control signal indicative of vertical blanking and an E_B video control signal indicative of horizontal blanking as respective control inputs to said instruction decode means.