Process for forming LDD MOS/CMOS structures

• US 4,703,551 A
• Filed: 01/24/1986
• Issued: 11/03/1987
• Est. Priority Date: 01/24/1986
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: NCR Corporation
• Inventors: Miller, Gayle W., Szluk, Nicholas J.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Thomas, Tom
• Application Number:
  US06/822,075
• Time in Patent Office: 648 Days
• Field of Search: 29/571, 29/576 W, 29/591, 357/23, 357/52, 357/47, 357/71, 148/1.5
• US Class Current: 438/220
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A process for selectively forming NMOS/PMOS/CMOS integrated circuits and for selectively incorporating any or all of lightly doped drain-source (LDD) regions, sidewall gate oxide structures, and guard band regions.

Claims

1. A process for forming an NMOS integrated circuit structure incorporating lightly doped drain/source structure, drain/source guard bands and oxide sidewall structures, comprising:

forming a gate structure for the NMOS device having an overlying overhang mask defining underlying regions adjacent the gate structure as source and drain;

preferentially forming a sidewall oxide layer from the highly doped NMOS gate structure at a relatively low temperature and to a correspondence with the overhang mask;

subjecting the structure to an n-type implantation in the presence of the overhang mask to form relatively heavily doped n-type source and drain regions in self-alignment with the overhang mask;

etching the sidewall oxide layer ot reduce the thickness thereof;

removing the overhang mask;

implanting n-type ions in the MNOS active area to from a relatively shallow lightly doped regions in self-alignment with the NMOS gate between the gate and the n⁺ source and drain regions; and

implanting p-type ions at an intermediate dose to form p-type guard band regions at the NMOS lightly doped drain-source regions.

2. A process for forming a PMOS integrated circuit structure incorporating lightly doped drain/source structure, drain/source guard bands and oxide sidewall structures, comprising:

forming a gate structure for the PMOS device having an overlying overhang mask defining underlying region adjacent the gate structure as source and drain regions;

preferentially forming a sidewall oxide layer from the PMOS gate structures at a relatively low temperature and to a correspondence with the overhang mask;

subjecting the structure to a p-type ion implantation in the presence of the overhang mask to form relatively heavily doped p-type sourve and drain regions in self-alignment with the overhang mask;

etching the sidewall oxide layer to reduce the thickness thereof;

removing the overhang mask;

implanting n-type ions at a relatively light dose to form a n-type guard band regions in self-alignment with the PMOS gate between the gate and the p⁺ source and drain regions and about the associated regions where lightly doped drain-source regions are formed; and

implanting the structure with p-type species at a selected energy and doe to form lightly doped p-type drain-source diffusions in said accociated regions.

3. A process for forming a complementary PMOS and NMOS integrated circuit structure incorporating lightly doped drain and source (LDD) structures, and comprising:

forming a gate sturcture for each device having an overlying overhang mask defining underlying regions adjacent the gate structure as source and drain regions;

preferentially forming sidewall oxide layers to a correspondence with the overhang masks;

doping the NMOS source and drain regions with n-type dopant in the presence of the NMOS overhang mask to form the heavily doped n-type source and drain regions in self-alignment with the NMOS overhang mask;

selectively narrowing the thickness of the NMOS sidewall oxide layer;

removing the NMOS overhang mask;

relatively lightly doping the NMOS active areas adjacent the gate structure with n-type dopant to form LDD regions in self-alignment with the NMOS gate between the gate and highly doped source and drain regions;

selectively doping the PMOS source and drain regions with p-type dopant in the presence of the PMOS overhang mask to form the heavily oped p-type source and drain regions in self-alignment with the PMOS overhang mask;

selectively narrowing the thickness of the PMOS sidewall oxide layer;

removing the PMOS overhang mask; and

relatively lightly doping the PMOS active areas adjacent the gate structure with p-type dopant to form LDD structure in self-alignment with the PMOS gate between the gate and the lighly doped source and drain regions.

4. The process of claim 3 wherein after removal of the PMOS overhang mask, the structure is selectively doped with n-type impurities to form guard band region for the PMOS LDD structures.

5. The process of claim 4 wherein the PMOS LDD doping step is a blanket doping step for simultaneously forming (a) p-type guard bands for the NMOS LDD structures and (b) the p-type LDD structures for the PMOS structures.

6. A process for forming a complementary PMOS and NMOS integrated circuit structure incorporting LDD structures, guard band structures and oxide sidewall structures, comprising:

(1) forming a gate structure for the PMOS and NMOS devices having an overlying overhang mask defining underlying regions adjacent the gate structure as source and drain regions;

(2) subjecting the structure to an oxidizing ambient at a relatively low temperature to preferentially form a sidewall oxide layer on the NMOS and PMOS gate structure to a correspondence with the overhang masks;

(3) selectively implanting the NMOS source and drain regions to a relatively heavy n⁺ concentration in self-alignment with the NMOS overhang mask;

(4) selectively and partially etching the NMOS sidewall oxide to reduce the thickness thereof to thereby provide a predetermined thickness of insulation between the NMOS gate and the associated heavily doped source and drain regions;

(5) removing the overhang mask;

(6) selectively implanting n-type dopant into the NMOS active area using a relatively low dose to form n-type LDD regions in self-alignment with the NMOS gate between the gate and the heavily doped NMOS source and drain regions;

(7) selectively implanting the PMOS source and drain regions to a relatively heavy p⁺ doping concentration in self-alignment with the PMOS overhang mask;

(8) selectively and partially etching the thickness of the PMOS sidewall oxide to reduce the thickness thereof and thereby provide a predetermined thickness of insulation between the PMOS gate and the associated heavily doped source and drain regions;

(9) removing the PMOS overhang mask;

(10) selectively implanting n-type dopant using a relatively low dose to form n-type guard band regions associated PMOS LDD regions in self-alignment with the PMOS gate and between the gate and the heavily doped PMOS source and drain regions; and

(11) blanket implanting the CMOS structure with p-type dopant using a relatively low dose to simultaneously form guard bands about the NMOS n-type LDD structures and to form p-type LDD structure in said PMOS LDD regions.

7. A process for forming a complementary PMOS and NMOS integrated circuit structure incorporating LDD structures, guard band structures and oxide sidewall structures, comprising:

(1) forming a gate structure for the PMOS and NMOS devices having an overlying overhang mask defining underlying regions adjacent the gate structure as source and drain regions;

(2) subjecting the structure to an oxidizing ambient at a relatively low temperature to preferentially form a relatively thick sidewall oxide on the highly doped NMOS and PMOS gate structures to a correspondence with the overhang masks;

(3) masking the PMOS device active area;

(4) implanting the NMOS source and drain regions to a relatively heavy n⁺ concentration in self-alignment with the NMOS overhang mask;

(5) selectively etching the NMOS sidewall oxide to reduce the thickness thereof and provide a predetermined thickness of insulation between the NMOS gate and the associated source and drain regions;

(6) removing the NMOS overhang mask;

(7) selectively implanting n-type ions in the NMOS active area using a relatively low energy and dose to form shallow lightly doped LDD regions in self-alignment with the NMOS gate between the gate and the n⁺ NMOS source and drain regions;

(8) removing the mask from the PMOS device active area;

(9) masking the NMOS device active area;

(10) implanting the PMOS source and drain regions to a relatively heavy p⁺ doping concentration in self-alignment with the PMOS overhang maks;

(11) selectively etching the PMOS sidewall oxide to reduce the thickness thereof and thereby provide a predetermined thickness of insulation between the PMOS gate and the associated source and drain regions;

(12) removing the PMOS overhang mask;

(13) selectively implanting n-type species using a relatively low energy and dose to thereby form n-type guard band regions about associated PMOS LDD regions in self-alignment with the PMOS gate and between the gate and the p⁺ PMOS source and drain regions; and

(14) blanket implanting the structure with p-type species using a relatively low energy and dose to simultaneously form a guard band regions about the NMOS LDD regions and the LDD regions in the PMOS LDD structures.