Phase difference measurement apparatus and method

• US 4,704,574 A
• Filed: 08/26/1986
• Issued: 11/03/1987
• Est. Priority Date: 08/26/1986
• Status: Expired due to Fees

• Current Assignee: RCA Corporation
• Original Assignee: RCA Corporation
• Inventors: Nossen, Edward J.
• Primary Examiner(s): Tokar, Michael J.
• Application Number:
  US06/900,525
• Time in Patent Office: 434 Days
• Field of Search: 324/83 R, 324/83 A, 324/83 D, 324/77 R, 328/133, 328/134, 328/155, 342/60
• US Class Current: 324/76.82
• CPC Class Codes: G01R 25/08 by counting of standard pulses

Abstract

An arrangement for coarse and vernier measuring of the delay or phase shift introduced by a delay path by generating a recurrent pseudorandom signal at an original chip clock rate derived from a reference clock. At the receiving end of the delay path, a delay locked loop regenerates the chip clock and the pseudorandom signal at a phase established by the delay. The coarse count is measured by the number of chip clock cycles. The vernier delay is measured in terms of a fractional portion of a chip clock cycle. The vernier measurement is made by starting a counter which counts reference clock signals in response to a coincidence of the original chip clock and the reference clock, and by ending counting and latching the count in response to coincidence of the regenerated chip clock and the reference clock.

Claims

1. Apparatus for measuring the phase difference between two signals, comprising:

a reference clock signal generator having a reference frequency;

a first chip clock signal generator for generating a first chip clock signal which is slaved to said reference clock signal at a first chip frequency which is a multiple of said reference frequency, said multiple being a ratio of integers;

first counting means coupled to said first chip clock signal generator for dividing said first chip frequency to produce a first count signal indicative of the count and for being reset to zero and for producing a first reset signal at a predetermined integer count;

first pseudorandom waveform generating means coupled to said first chip clock signal generator and to said first counting means, and adapted to be coupled to phase shifting means, for generating and applying to said phase shifting means a particular pseudorandom waveform at said first chip frequency, and for being reset to an initial state by said first reset signal;

latching means including a latch control input terminal, said latching means being coupled to said first counting means for receiving said first count signal and for latching said first count signal under control of a second reset signal applied to said latch control input terminal;

correlation receiving means adapted to be coupled to said phase shifting means for receiving phase shifted pseudorandom waveform therefrom at said chip frequency, for generating a delay loop control signal which is related to the phase offset between a replica of said pseudorandom waveform and said phase shifted pseudorandom waveform;

a slaved chip clock signal generator coupled to said correlation receiving means for receiving said delay loop control signal for generating a slaved chip clock signal at a controllable frequency;

second counting means coupled to said slaved chip clock signal generator and to said latch control input terminal of said latching means for receiving said slaved chip clock for dividing said frequency by said predetermined integer, for being reset to zero at said predetermined integer count, and for producing said second reset signal at each said predetermined integer count, said second reset signal being coupled to said latch control input terminal of said latching means for latching said latching means;

second pseudorandom waveform generating means coupled to said slaved chip clock signal generator, to said second counting means, and to said correlation receiving means for generating and applying said particular pseudorandom waveform to said correlation receiving means at said controllable frequency of said slaved chip clock signal, and for being reset to said initial state by said second reset signal, said correlation receiving means, slaved chip clock signal generator, second counting means and second pseudorandom waveform generator together forming a delay locked loop by which said controllable frequency is made equal to said first chip frequency and also by which said second reset signal occurs at a time relative to said first reset signal which is controlled by the time delay of said phase shifting means, whereby said latching of said latching means by said second reset signal is delayed relative to said reset of said first counting means and latches a gross count in said latching means equal to said time delay within the resolution accuracy provided by said first chip clock frequency;

first and second AND gate means, each including first and second input terminals;

first coupling means coupled to said reference clock signal generator, to said first and slaved chip clock signal generators for applying reference pulses controlled by said reference clock signal generator to said first input terminals of said first and second AND gate means, for applying first chip pulses controlled by said first chip clock signal generator to said second input terminal of said first AND gate means, and for applying slaved pulses controlled by said slaved chip clock signal generator to said second input terminal of said second AND gate means, for producing a START signal from said first AND gate means at each coincidence of one of said first chip pulses and one of said reference pulses, which coincidence of said first chip pulses and said reference pulses recur at a lower frequency than either of said reference frequency and said first chip frequency, and for producing a STOP signal from said second AND gate means at each coincidence of one of said slaved pulses and one of said reference pulses, which coincidence of said slaved pulses and said reference pulses recur at said lower frequency, whereby a said STOP signal occurs at a time after a said START signal equal to the product of a time between successive START signals multiplied by a quotient, said quotient being the ratio of first and second time differences, said first time difference being equal to the time between the occurrence of said second reset signal and that one of said first chip clock signals immediately preceding said second reset signals, and said second time difference being the time between two successive first chip clock signals, whereupon the exact time of occurrence of said second reset signal between two successive first chip clock signals is proportional to the delay of said STOP signals after said START signal relative to the reciprocal of said lower frequency;

third counting means coupled to said reference clock signal generator and responsive to an ENABLE signal for counting said reference clock signals for generating a fine count;

toggle means coupled to said first and second AND gate means and to said third counting means for assuming a first state in response to the first of one or more successive START signals, and for assuming a second state upon the occurrence of the first STOP signal occurring after a previous START signal for, when in said first state, generating and applying said ENABLE signal to said third counting means for initiating counting of said reference clock signals in response to said first state, and in said second state for ceasing production of said ENABLE signal, thereby causing cessation of counting of said reference clock pulses by said third counting means, whereby said fine count in said third counting means at the time of occurrence of said first STOP signal occurring after a previous START signal provides additional information relative to said phase to a greater resolution than that provided by said first chip clock frequency.

2. Apparatus according to claim 1, further comprising:

second latching means coupled to said third counting means and to said toggle means and responsive to the initiation of said second state for latching said fine count.

3. Apparatus according to claim 1, wherein:

said third counting means begins counting in response to said ENABLE signal, and continues to count until receipt of a DISABLE signal; and

further comprising;

fourth counting means coupled to said toggle means and to said third counting means for counting a predetermined number of said ENABLE signals before generating and applying said DISABLE signal to said third counting means.

4. Apparatus according to claim 2, wherein each word of said fine count generated by said third counting means uniquely represents in a nonmonotonic progression a particular value of said quotient, and further comprising:

memory means coupled to said second latching means, said memory means including memory locations addressed by each word of said fine count, each said memory location being preprogrammed with a word which represents a particular value of said quotient selected for conversion of said nonmonotonic progression to a monotonic progression.

5. A method for measuring the round-trip delay of a signal path, comprising the steps of:

generating a reference clock signal having a reference frequency;

slaving an original chip clock signal to said reference clock signal at a chip clock frequency which is a multiple of said reference frequency, where said multiple is the ratio of integers;

modulo counting said original chip clock signal to produce a count signal and to produce first reset signals at a predetermined count;

generating chips of a particular pseudorandom signal at said chip clock frequency, said particular pseudorandom signal recurring in response to said first reset signals to form a recurrent particular pseudorandom signal;

applying said recurrent particular pseudorandom signal to a first end of said signal path;

receiving said recurrent particular pseudorandom signal from said signal path to form a received signal, which is said recurrent particular pseudorandom signal delayed by the delay of said signal path;

generating a replica chip clock signal at a frequency near said chip clock frequency;

modulo counting said replica chip clock signal to produce second reset signals at said predetermined count;

generating chips of a second pseudorandom signal having the same pattern a said particular pseudorandom signal in response to said replica chip clock signal, said pseudorandom signal recurring in response to said second reset signal;

comparing the phase of said received signal with said second pseudorandom signal to form a control signal;

controlling the frequency of said replica chip clock signal in response to said control signal for forcing said frequency near said chip clock frequency to equal said chip clock frequency, whereby said second reset signal is delayed from said first reset signal by said delay of said signal path;

storing the value of said count signal in response to said second reset signal to provide a coarse indication of said delay of said signal path;

generating a START signal at each coincidence of said original chip clock signal and said reference clock signal;

beginning counting of said reference clock signal in a counter in response to one of said START signals;

generating a STOP signal at each coincidence of said replica chip clock signal and said reference clock signal;

ending counting of said reference clock signal in response to one of said STOP signals occurring after one of said START signals to thereby produce a fine indication of the increment of said delay of said path over the value of said delay of said signal path provided by said coarse indication; and

utilizing the information of said coarse and fine indications to provide a final indication of said delay of said signal path.

6. A method according to claim 5, wherein said step of ending counting of said reference clock signal further comprises the steps of:

blocking application of said STOP signals to said counter;

counting a predetermined number of said STOP signals to produce an unblocking signal; and

ceasing said blocking in response to said unblocking signals.