Gated demodulator for shaped BPSK signals

• US 4,704,582 A
• Filed: 10/07/1986
• Issued: 11/03/1987
• Est. Priority Date: 10/07/1986
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Broughton, Christopher D., Dixon, Charles E.
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US06/916,354
• Time in Patent Office: 392 Days
• Field of Search: 329/50, 329/104, 329/110, 329/122, 329/124, 329/131, 329/132, 329/136, 329/178, 455/210, 455/212, 455/222, 455/223, 455/224, 455/260, 455/295, 455/265, 455/309, 455/312, 375/81, 375/82, 375/83, 375/94, 375/99, 375/104, 375/120
• US Class Current: 329/308
• CPC Class Codes: H04L 2027/0067 Phase error detectors
• CPC Class Codes: H04L 2027/0079 Switching between loops
• CPC Class Codes: H04L 27/2273 associated with quadrature demodulation, e.g. Costas loop

Abstract

A demodulator for shaped BPSK signals that utilizes switches which have switching control means designed to eliminate unwanted Q channel signal power and unwanted carrier phase error signal power by opening the switches during the phase transition portions of the shaped BPSK signals. The switching control means close the switches during non-transitional portions of the shaped BPSK signals.

Claims

1. A method of demodulating a shaped BPSK input signal having linear phase transitions between destination phase dwells comprising the steps of chopping out the portion of the BPSK signal caused by the linear phase transition of the shaped BPSK input signal, and demodulating the destination phase dwells.

2. A demodulator comprising:

an input node capable of receiving a modulated signal;

first and second multiplier means connected to said input node;

a first low pass filter circuit coupled to said first multiplier means;

a second low pass filter circuit coupled to said second multiplier means;

switching means coupled between said first multiplier means and said first low pass filter and also between said second multiplier means and said second low pass filter;

third multiplier means having inputs supplied by said first low pass filter circuit and said second low pass filter circuit;

a loop filter coupled to said third multiplier means;

a voltage controlled oscillator connected between said loop filter and said second multiplier means;

a ninety degree phase shifter coupled between said first multiplier and said voltage controlled oscillator;

a data output node positioned between said second multiplier means and said switching means; and

switching control means between said data output node and said switching means.

3. A demodulator as recited in claim 2 wherein said switching control means includes a bit synchronizer and a delay adjust.

4. A demodulator as recited in claim 2 additionally comprising a carrier lock detector circuit connected to the inputs of said third multiplier means.