High power MOSFET with low on-resistance and high breakdown voltage

• US 4,705,759 A
• Filed: 01/10/1983
• Issued: 11/10/1987
• Est. Priority Date: 10/13/1978
• Status: Expired due to Term

• Current Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Herman, Thomas, Lidow, Alexander
• Primary Examiner(s): SABA, WILLIAM
• Application Number:
  US06/456,813
• Time in Patent Office: 1,765 Days
• Field of Search: 29/571, 29/576 B, 29/578, 148/1.5, 148/187, 148/190, 357/23 VD, 357/20, 357/41, 357/52, 357/89, 357/91
• US Class Current: 438/268
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A high power MOSFET is disclosed in which two laterally spaced sources each supply current through respective channels in one surface of a semiconductor chip which are controlled by the same gate. The channels lead from the source electrodes to a relatively low resistivity region and from there to a relatively high resistivity epitaxially formed region which is deposited on a high conductivity substrate. The drain electrode may be either on the opposite surface of the chip or laterally displaced from and on the same side as the source regions. The epitaxially deposited semiconductor material immediately adjacent and beneath the gate and in the path from the sources to the drain has a relatively high conductivity, thereby to substantially reduce the on-resistance of the device without effecting the breakdown voltage of the device. The breakdown voltage of the device is substantially increased by forming a relatively deep p-type diffusion with a large radius in the n-type epitaxial layer beneath each of the sources.

Claims

1. The method of manufacture of a high power MOSFET device which comprises the steps of:

(a) forming an insulation coating on the upper surface of a flat chip of a monocrystalline semiconductor of one of the conductivity types;

(b) opening at least first and second spaced windows in said insulation coating which have at least first respective portions thereof which are elongated and parallel to one another;

(c) applying impurity carriers of a conductivity type opposite said one conductivity type to said upper surface which is exposed by said first and second windows and heating said chip to cause said carriers to diffuse into said chip to form first and second respective regions of said opposite conductivity type in said chip which have a first depth;

(d) opening at least third and fourth spaced windows in any insulation coating on said upper surface which are coextensive with and adjacent to said first and second windows;

said third and fourth windows being disposed inwardly of the space between said first and second windows and being laterally removed from atop said first and second regions respectively;

(e) applying impurity carriers of said opposite conductivity type to said upper surface which is exposed by said third and fourth windows and heating said chip to cause said carriers to diffuse into said chip to form third and fourth respective regions of said opposite conductivity type which are continuous with the adjacent sides of said first and second regions respectively but are shallower than said first and second regions;

the opposite edges of parallel portions of said third and fourth regions being laterally diffused until they are spaced from one another by a given distance by a common neck region of said one conductivity type of said chip;

(f) applying impurity carriers of said one conductivity type to said upper surface which is exposed by said third and fourth windows and heating said chip to cause said carriers from said one conductivity type to diffuse into said third and fourth regions for only a portion of the depth and width of said third and fourth regions to define first and second source regions;

said first and second source regions having facing edges which are spaced from said common neck region, thereby to define first and second channel regions in said third and fourth regions respectively;

(g) and forming an insulated gate means atop said upper surface and over said first and second channel regions, and forming source electrode means on said source regions and drain electrode means on the surface of said chip which is opposite said upper surface.

2. The method of claim 1 wherein said impurity carriers of said opposite conductivity type which are applied through said first and second windows, and said impurity carriers of said opposite conductivity type which are applied through said third and fourth windows, are each applied by ion implantation.

3. The method of claim 1 wherein said chip has an epitaxial layer thereon which extends to said upper surface and wherein all of said regions are contained within said epitaxial layer.

7. The method of claim 1, 2 or 3 wherein, following the step of forming said first and second regions of said opposite conductivity type, impurity carriers of said one conductivity type are applied to at least selected regions of said upper surface to cause impurities of said one conductivity type to diffuse into said chip to form relatively lightly doped regions of said one conductivity type which are disposed laterally within said common neck region and which extend to said upper surface of said chip.

4. The method of manufacture of a high power MOSFET device which comprises the steps of:

(a) forming an insulation coating on the upper surface of a flat chip of a monocrystalline semiconductor of one of the conductivity types;

(b) opening at least first and second spaced windows in said insulation coating which have at least first respective portions thereof which are elongated and parallel to one another;

(c) applying impurity carriers of a conductivity type opposite said one conductivity type to said upper surface which is exposed by said first and second windows and heating said chip to cause said carriers to diffuse into said chip to form first and second respective regions of said opposite conductivity type in said chip which have a first depth;

(d) opening at least third and fourth spaced windows in said insulation coating on said upper surface which are coextensive with and adjacent to said first and second windows respectively;

said third and fourth windows being disposed inwardly of the space between said first and second windows and being laterally removed from atop said first and second regions respectively;

(e) applying impurity carriers of said one conductivity type to said upper surface through said third and fourth windows and heating said chip to cause said impurity carriers of said one conductivity type to diffuse into said chip to form relatively highly doped regions of said one conductivity type which spread laterally until they join one another in a common neck region beneath said insulation coating which is between said third and fourth windows;

(f) applying impurity carriers of said opposite conductivity type to said upper surface which is exposed by said third and fourth windows and heating said chip to cause said carriers to diffuse into said chip to form third and fourth respective regions of said opposite conductivity type which are continuous with the adjacent sides of said first and second regions respectively but are shallower than said first and second regions;

the opposite edges of parallel portions of said third and fourth regions being laterally diffused until they are spaced from one another by a given distance by said common neck region of said one conductivity type of said chip;

(g) applying impurity carriers of said one conductivity type to said upper surface which is exposed by said third and fourth windows and heating said chip to cause said carriers from said one conductivity type to diffuse into said third and fourth regions for only a portion of the depth and width of said third and fourth regions to define first and second source regions;

said first and second source regions having facing edges which are spaced from said common neck region, thereby to define first and second channel regions in said third and fourth regions respectively;

(h) and forming an insulated gate means atop said upper surface and over said first and second channel regions, and forming source electrode means on said source regions and drain electrode means on the surface of said chip which is opposite said upper surface.

5. The method of claim 4 wherein said impurity carriers of said opposite conductivity type which are applied through said first and second windows, and said impurity carriers of said opposite conductivity type which are applied through said first and second windows, and said impurity carriers of said opposite conductivity type which are applied through said third and fourth windows, are each applied to said upper surface by ion implanation.

6. The method of claim 4 wherein said chip has an epitaxial layer thereon which extends to said upper surface and wherein all of said regions are contained within said epitaxial layer.