Programmable interval timer with lock means

• US 4,705,970 A
• Filed: 02/04/1985
• Issued: 11/10/1987
• Est. Priority Date: 02/04/1985
• Status: Expired due to Term

• Current Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: American Telephone & Telegraph Company (AT&T, Inc.)
• Inventors: Turnpaugh, George F.
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): Davis, B. P.
• Application Number:
  US06/697,880
• Time in Patent Office: 1,009 Days
• Field of Search: 307/517, 307/518, 307/362, 307/600, 328/109-110, 377/84, 371/62
• US Class Current: 327/31
• CPC Class Codes: G04G 15/003 acting only at one preselected time or during one adjustable time interval
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs

Abstract

A programmable interval timer (100) for generating an error signal when a timing signal is received outside a predetermined time frame. The timer includes a timer circuit (104) having programmable minimum and maximum timing intervals for determining the predetermined time frame. These timing intervals are programmed into the timer circuit in response to data input signals indicative of the timing intervals from, for example, a microprocessor. The timer circuit generates one output signal when the time interval between two consecutively received timing signals is less than the minimum timing interval. Another output signal is generated when the time interval is greater than the maximum timing interval. An error signal latch generates the error signal when it receives either one of the two timer circuit output signals. Also included is a lock circuit (102) for preventing the timer circuit from responding to any data input signals after the first timing signal is received. Lastly, an indicator latch (103) is also provided to indicate to, for example, a central processing unit that an error signal has been sent to the microprocessor. A reset signal from the central processing unit resets the indicator latch and unlocks the lock circuit to reprogram the minimum and maximum timing intervals.

Claims

1. A programmable interval timer for generating an error signal when a timing signal is received outside a predetermined time frame, comprising:

timer means having minimum and maximum timing intervals determining said predetermined time frame and responsive to first and second data input signals for setting said minimum and maximum timing intervals, respectively, and further responsive to first and second timing signals for generating a first output signal when the time interval between said first and second timing signals is less than said minimum timing interval and a second output signal when the time interval between said first and second timing signals is greater than said maximum timing interval;

latch means for generating said error signal in response to one of said first and second output signals; and

lock means connected to said timer means and responsive to a first receipt of one of said first and second timing signals for preventing said timer means from responding to one of said first and second data input signals.

2. The timer of claim 1 wherein said timer means comprises first counter means having said minimum timing interval and responsive to said first and second timing signals for generating said first output signal when the time interval between said first and second timing signals is less than said minimum timing interval and second counter means having said maximum timing interval and responsive to said first and second timing signals for generating said second output signal when the time interval between said first and second timing signals is greater than said maximum timing interval.

3. The timer of claim 1 wherein said timer means further comprises register means for storing said first and second input signals.

4. A lockable, programmable interval timer comprising:

programmable means having a minimum timing interval and responsive to a data input signal for setting said minimum timing interval and further responsive to first and second timing signals for generating an error signal when the time interval between said first and second timing signals is less than said minimum timing interval, and

lock means when in a locked state for preventing said programmable means from responding to any data input signal, said lock means assuming said locked state in response to said first timing signal.

5. A lockable, programmable interval timer comprising:

programmable means having a maximum timing interval and responsive to a first data input signal for setting said maximum timing interval and further responsive to first and second timing signals for generating an error signal when the time interval between said first and second timing signals is greater than said maximum timing interval, and

lock means when in a locked state for preventing said programmable means from responding to any data input signal, said lock means assuming said locked state in response to said first timing signal.

6. The timer of claim 5 wherein said programmable means also has a minmum timing interval and is responsive to a second data input signal for setting said minimum timing interval and is further responsive to said first and second timing signals for also generating said error signal when the time interval between said first and second timing signals is less said minimum timing interval.

7. The timer of claim 5 wherein said lock means has an unlocked state and is further responsive to a reset signal for assuming said unlocked state, said programmable means being responsive to said first and second data input signals when said lock means is in said unlocked state.

8. A lockable, programmable interval timer for generating an error signal when a timing signal is outside a predetermined time frame, comprising:

programmable means having minimum and maximum timing intervals determining said predetermined time frame and responsive to first and second data input signals for setting said minimum and maximum timing intervals, respectively, and further responsive to first and second timing signals for generating said error signal when at least one of said first and second timing signals is received outside of said predetermined time frame, and

lock means connected to said programmable means and when in a locked state for preventing said programmable means from responding to any data input signal, said lock means assuming said locked state in response to a first receipt of one of said timing signals.

9. A lockable, programmable interval timer for generating an error signal when a timing signal is outside a predetermined time frame, comprising:

timer means having minimum and maximum timing intervals determining said predetermined time frame and responsive to first and second data input signals for setting said minimum and maximum timing intervals, respectively, and further responsive to first and second timing signals for generating a first output signal when the time interval between said first and second timing signals is less than said minimum timing interval and a second output signal when the time interval between said first and second timing signals is greater than said maximum timing interval;

latch means for generating said error signal in response to one of said first and second output signals; and

lock means connected to said timer means and when in a locked state for preventing said timer means from responding to any data input signal, said lock means assuming said locked state in response to a first receipt of one of said timing signals.

10. The timer of claim 9 wherein said timer. means comprises first counter means having said minimum timing interval and responsive to said first and second timing signals for generating said first output signal when the time interval between said first and second timing signals is less said minimum timing interval and second counter means having said maximum timing interval and responsive to said first and second timing signals for generating said second output signal when the time interval between said first and second timing signals is greater than said maximum timing interval.

11. The timer of claim 10 wherein said timer means further comprises register means for storing said first and second data signals.

12. The timer of claim 9 wherein said lock means has an unlocked state and is further responsive to a reset signal for assuming said unlocked state, said programmable means being responsive to said first and second data input signals when said lock means is in said unlocked state.