Differential amplifier having ratioed load devices

• US 4,706,036 A
• Filed: 12/22/1986
• Issued: 11/10/1987
• Est. Priority Date: 12/22/1986
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Rebeschini, Michael E.
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/944,404
• Time in Patent Office: 323 Days
• Field of Search: 330/253, 330/255, 330/257, 330/264, 330/269, 330/307
• US Class Current: 330/253
• CPC Class Codes: H03F 2203/30021 A capacitor being coupled in a feedback circuit of a SEPP amplifier
• CPC Class Codes: H03F 2203/30057 the SEPP power transistors are realised as paralleled FETs, i.e. the push or the pull transistor
• CPC Class Codes: H03F 2203/30126 the push side of the SEPP amplifier has an extra drive inverter stage to control this push side
• CPC Class Codes: H03F 2203/30138 the push transistor of the asymmetrically driven SEPP amplifier being a driven current mirror
• CPC Class Codes: H03F 2203/45182 the differential amplifier contains one or more cascode current mirrors in the load
• CPC Class Codes: H03F 2203/45221 the output signal being taken from the two complementary outputs of the differential amplifier
• CPC Class Codes: H03F 2203/45631 the LC comprising one or more capacitors, e.g. coupling capacitors
• CPC Class Codes: H03F 2203/45676 the LC comprising one cascode current mirror
• CPC Class Codes: H03F 3/3022 CMOS common source output SEPP amplifiers H03F3/3008 takes precedence
• CPC Class Codes: H03F 3/3027 using a common source driving stage, i.e. inverting stage
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence

Abstract

A differential amplifier is provided which has a low systematic offset voltage and a small variation in quiescent current with respect to variations in processing and temperature while providing low input referred noise and good output drive capability. Each transistor of a differential input pair of transistors is coupled to a plurality of series-connected transistors which are fabricated with substantially equal control electrode dimensions to form composite load tranistors. An output stage having conventional source and sink transistors is coupled to the differential pair of transistors. The sink transistor is implemented as a composite transistor by a plurality of parallel-connected transistors, each also having substantially the same control electrode dimension. Since all the ratioed transistors have equal control electrode dimensions, variations over processing and temperature are minimized. The composite load transistors have a large effective gate length for low input referred noise, and the composite transistor of the output stage has a small effective gate length to provide good drive capability.

Claims

1. A differential amplifier having a differential input pair of transistors for receiving first and second input voltages and providing an output voltage proportional to a differential of the first and second input voltages, further comprising:

a plurality of series-connected load transistors coupled to each transistor of the differential input pair of transistors, said series-connected load transistors each having a control electrode connected together and to one transistor of the input of transistors, each of said series-connected load transistors having substantially equal first predetremined ocntrol electrode width and length dimensions which form a first composite predetermined control electrode dimension; and

an output stage coupled to the differential input pair of transistors and to the first plurality of series-connected transistors, said output stage having a source output transistor and a sink output transistor, the sink output transistor being implemented by a plurality of parallel-connected sink transistors, each of said parallel-connected sink transistors having substantially the same first predetermined control electrode width and length dimensions to form a second composite predetermined control electrode dimension ratioed in a predetermined ratio with the first composite predetermined control electrode dimension.

2. The differential amplifier of claim 1 wherein the first composite predetermined control electrode dimension has a first width substantially smaller than a second electrode dimension, and has a first length substantially larger than a second length of the second composite predetermined control electrode dimension.

3. The differential amplifier of claim 1 further comprising:

a drive stage coupled to the load transistors and to the output stage, for improving output slew rate of the differential amplifier, said drive stage having a transistor of a first conductivity type which is size ratioed with the source output transistor by having substantially equal second predetermined control electrode width and length dimensions, and having a transistor of a second conductivity type which is size ratioed with each of the sink transistors by having a control electrode dimension substantially equal to the first predetermined control electrode dimension.

4. A method of providing a process insensitive differential amplifier having improved offset voltage compensation, comprising the steps of:

providing a differential input pair of transistors for receiving differential input voltages;

coupling a plurality of series-connected load transistors to each transistor of the input pair of transistors, the load transistors each having a control electrode connected together and to a first transistor of the input pair of transistors, each control electrode having a first predetermined control electrode width/length dimension to form a first composite predetermined control electrode dimension; and

coupling an output stage to the load transistors, said output stage providing an output voltage of the differential amplifier and having a source transistor coupled in series with a sink transistor, said sink transistor implemented by a plurality of parallel-connected transistors, the parallel-connected transistors each having a control electrode connected together and to a second transistor of the input pair of transistors, each control electrode having a second predetermined control electrode width/length dimension to form a second composite predetermined control electrode dimension ratioed in a predetermined ratio with the first composite predetermined control electrode dimension.

5. A process insensitive differential amplifier having improved offset voltage correction, comprising:

a first transistor of a first conductivity type having a first current electrode coupled to a power supply voltage, a second current electrode, and a control electrode for receiving a bias voltage;

a second transistor of the first conductivity type having a first current electrode coupled to the second current electrode of the first transistor, a control electrode for receiving a first input voltage, and a second current electrode;

a third transistor of the first conductivity type having a first current electrode coupled to the second current electrode of the first transistor, a control electrode for receiving a second input voltage, and a second current electrode for providing an output terminal;

a first plurality of transistors of a second conductivity type coupled in series between the second current electrode of the second transistor and a second power supply voltage, each of said transistors of the first plurality having a control electrode connected together and to the second current electrode of the second transistor with a first predetermined control electrode dimension to form a first composite predetermined control electrode dimension;

a second plurality of transistors of the second conductivity type coupled in series between the second current electrode of the third transistor and the second power supply voltage, said first plurality being equal in number to the second plurality, and each transistor of the second plurality having a control electrode connected together and to the second current electrode of the third transistor and having the first predetermined control electrode dimension to form the first composite predetermined control electrode dimension; and

an output stage coupled to the output terminal, said output stage having a sink transistor comprising a third plurality of transistors of the second conducitvity type coupled in parallel, each of the transistors of said third plurality also having a control electrode with the substantailly equal first predetermined control electrode dimension to form a second composite predetermined control electrode dimension ratioed in a predetermined ratio with the first composite predetermined control electrode dimension.

6. The differential amplifier of claim 5 further comprising:

a fourth transistor of the second conductivity type having a first current electrode, a control electrode coupled to the second current electrode of the second transistor, and a second current electrode coupled to the second power supply voltage, said fourth transistor having a control electrode dimension substantially equal to the first predetermined control electrode dimension; and

a fifth transistor of the first conductivity type having a first current electrode coupled to the first power supply voltage, a second current electrode connected to a control electrode thereof and coupled to both the first current electrode of the fourth transistor and to the output stage, said fourth and fifth transistors providing a faster output slew rate for the differential amplifier.