Serial data bus for intermodule data communications

• US 4,706,082 A
• Filed: 02/24/1986
• Issued: 11/10/1987
• Est. Priority Date: 02/24/1986
• Status: Expired due to Term

• Current Assignee: Siemens VDO Automotive Electronics Corp (Continental AG)
• Original Assignee: Chrysler Motors Corp (Stellantis NV)
• Inventors: McCambridge, John M., Miesterfeld, Frederick O. R., Fassnacht, Ronald E.
• Primary Examiner(s): Weldon, Ulysses
• Application Number:
  US06/832,908
• Time in Patent Office: 624 Days
• Field of Search: 340/825.5, 340/825.51, 370/85, 370/89, 370/95
• US Class Current: 710/240
• CPC Class Codes: F02D 41/266 the computer being backed-up or assisted by another circuit, e.g. analogue
• CPC Class Codes: G06F 13/374 using a self-select method with individual priority code comparator
• CPC Class Codes: H04L 12/40032 Details regarding a bus interface enhancer
• CPC Class Codes: H04L 12/413 with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]

Abstract

A bus interface integrated circuit is presented which utilizes an arbitration detector, a collision detector and a contention permitting differential transceiver to work with a serial communication interface port on a microprocessor to determine between contending messages which message gains access to the communication bus by using the value or priority of the ID byte without losing bus time.

Claims

1. A communication system for the transmission of data messages through a data bus between two or more user microprocessors coupled to the data bus, the user microprocessors having a serial communications interface (SCI) port along with a clock port and an input/output port, the user microprocessors being coupled to the data bus by a bus interface integrated circuit, the bus interface integrated circuit comprising:

an arbitration detector;

a collision detector;

a bus driver;

a bus receiver;

and an idle detector;

a series circuit formed by the connection of the arbitration detector, collision detector and bus driver connected between the SCI port of the user microprocessor and the data bus to transmit data from the user microprocessor to the data bus;

the bus receiver connected between the data bus and the SCI port of the user microprocessor to receive data messages from the data bus to the user microprocessor;

the idle detector connected between the input port of the user microprocessor and individually to the arbitration detector and collision detector to monitor the data bus and detect when the data bus is idle and when the data bus is busy.

2. The bus interface integrated circuit of claim 1 further comprising:

a digital filter connected between the bus receiver and the SCI port of the user microprocessor to filter out noise from the data messages before being processed by other parts of the bus interface integrated circuit;

timing and synchronizing means to establish synchronizing and a baud rate timing signal for use by the arbitration detector, collision detector and idle detector comprising;

a clock divider to receive a clock pulse from the user microprocessor to generate a clock signal;

a word counter to accept the clock signal and present timing and synchronizing information to the arbitration detector and to the collision detector;

a stop bit detector to count and indicate when a start bit signal and level is present on the data bus;

a framing error detector to count and indicate when a start bit signal and level is present on the data bus;

an idle detector to monitor and indicate when the data bus is in an idle condition.