Circuit wiring disposed on solder mask coating

• US 4,706,167 A
• Filed: 12/17/1985
• Issued: 11/10/1987
• Est. Priority Date: 11/10/1983
• Status: Expired due to Fees

• Current Assignee: Telemark Incorporated
• Original Assignee: Telemark Incorporated
• Inventors: Sullivan, Donald F.
• Primary Examiner(s): Grimley, Arthur T.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/809,767
• Time in Patent Office: 693 Days
• Field of Search: 174/68.5, 361/398, 361/402, 361/406.8, 361/404, 361/411, 427/96, 430/315, 430/319, 430/312, 430/313, 324/73 PC, 29/847
• US Class Current: 361/774
• CPC Class Codes: H05K 1/0266 Marks, test patterns or identification means
• CPC Class Codes: H05K 1/0268 for electrical inspection or testing
• CPC Class Codes: H05K 1/117 Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
• CPC Class Codes: H05K 2201/09036 Recesses or grooves in insulating substrate recess in metallic substrate H05K2201/09745
• CPC Class Codes: H05K 2201/09436 Pads or lands on permanent coating which covers the other conductors
• CPC Class Codes: H05K 2201/09781 Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
• CPC Class Codes: H05K 2201/09845 Stepped hole, via, edge, bump or conductor
• CPC Class Codes: H05K 2201/09927 Machine readable code, e.g. bar code
• CPC Class Codes: H05K 2201/09936 Marks, inscriptions, etc. for information
• CPC Class Codes: H05K 2201/09981 Metallised walls
• CPC Class Codes: H05K 2203/025 Abrading, e.g. grinding or sand blasting deburring, rounding, bevelling or smoothing conductor edges H05K2203/0346
• CPC Class Codes: H05K 2203/054 Continuous temporary metal layer over resist, e.g. for selective electroplating
• CPC Class Codes: H05K 2203/056 Using an artwork, i.e. a photomask for exposing photosensitive layers
• CPC Class Codes: H05K 2203/0571 Dual purpose resist, e.g. etch resist used as solder resist, solder resist used as plating resist
• CPC Class Codes: H05K 2203/0577 Double layer of resist having the same pattern
• CPC Class Codes: H05K 2203/066 Transfer laminating of insulating material, e.g. resist as a whole layer, not as a pattern transferring an insulating pattern H05K2203/0537
• CPC Class Codes: H05K 2203/0759 Forming a polymer layer by liquid coating, e.g. a non-metallic protective coating or an organic bonding layer
• CPC Class Codes: H05K 3/0023 by exposure and development of a photosensitive insulating layer
• CPC Class Codes: H05K 3/045 by making a conductive layer having a relief pattern, followed by abrading of the raised portions
• CPC Class Codes: H05K 3/108 by semi-additive methods; masks therefor characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241
• CPC Class Codes: H05K 3/242 : characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
• CPC Class Codes: H05K 3/3452 : Solder masks
• CPC Class Codes: H05K 3/465 : by applying an insulating layer having channels for the next circuit layer
• CPC Class Codes: H05K 3/4661 : Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor other insulating materials H05K3/387
• CPC Class Codes: Y10T 29/49156 : with selective destruction of conductive paths

Abstract

In the manufacturing process for a printed wiring board a photopolymer insulation layer having a flat outer plateau surface is extended from the board substrate surface carrying the wiring pattern and provides access channels to a plurality of wiring pattern conductor pad areas. A patterned conductor layer disposed on the insulation layer surface including the sidewalls of the access channels thus electrically connects to the conductor pad areas. Circuit wiring pattern test current or plating currents are passed through the conductor layer pattern during the manufacturing process, and the conductor layer may thereafter be easily removed from the flat surface by sanding or the like. Permanently retained conductor layer portions, such as feasible by indenting the plateau surface, aid in expanding conductor surface areas at solder joint pads, or in increasing the density of circuit wires feasible in a given substrate board area. The conductor layer may provide indicia marking nomenclature patterns which are in dot matrix format to reduce capacitance coupling between wiring circuits on the board substrate.

Claims

1. In a printed wiring board assembly having an insulation photopolymer resist coating such as a solder mask layer disposed to extend upwardly from a conductive circuit wiring pattern on a printed wiring board substrate surface to cover a substantial portion of the substrate surface while leaving exposed through a resist coating conductor pads at predetermined circuit contact positions on the substrate surface, the improvement comprising in combination providing increased efficiency of circuit space usage with given board substrate dimensions thereby permitting additional circuit board patterns to be printed without increasing the substrate area, namely, a thin conductive circuit pattern on the substrate surface, said insulation resist coating consisting of a cured liquid photopolymer with a glossy flush surface formed by contact of a flat plate with the polymer in liquid form which is adhered to the substrate surface and presents a flush flat surface plateau with access channels downwardly extending thereinto to expose the conductor pads on the substrate surface and having a thin conductive coating on the channel sidewalls electrically contacting the exposed conductor pads, and a layer of conductive material disposed on the surface of said insulation coating in a pattern with controlled electronic coupling to the circuit board wiring pattern.

2. The assembly defined in claim 1 wherein the layer of conductive material comprises indicia marking nomenclature.

3. The assembly defined in claim 2 wherein the indicia marking nomenclature comprises dot matrix patterns thereby reducing capacitance coupling to conductor wires in said wiring pattern.

4. The assembly defined in claim 1 wherein the layer of conductive material comprises a conductive wiring pattern electrically connected to at least one of the circuit contact positions by means of said coating on the sidewalls.

5. The assembly of claim 4 wherein said pattern comprises an enlarged pad conductor surface area disposed in part on the insulation resist coating surface.

6. The assembly of claim 4 wherein said pattern comprises a set of test connector leads electrically connected to at least a portion of the circuit pad positions and leading to and forming connector terminals at the edge of the printed wiring board substrate.

7. The assembly of claim 4 including portions of the conductive material pattern disposed as indicia on said flat surface and electrically insulated from said wiring pattern.

8. The assembly of claim 7 wherein the indicia pattern is comprised of half tone dot patterns thereby serving to reduce capacitance coupling with circuit wiring patterns on the printed wiring board substrate.

9. The assembly defined in claim 1 wherein the wiring pattern is disposed in part on the insulation coating.

10. The assembly defined in claim 1 wherein the conductive circuit pattern coating on the surface of the substrate is covered in part by the resist insulation coating.

11. The assembly defined in claim 1 wherein a supplemental circuit wiring pattern electrically connected to the wiring pattern on the substrate surface is disposed in part on the surface of the insulation coating.

12. The assembly defined in claim 11 further comprising said resist coating disposed with a plurality of side by side surface portions, namely ridges on said substrate surface and spacings therebetween with the tops of the ridges defining a flat surface, conductor lines deposited in the spaces over the exposed surfaces therein to produce lines of a width greater than the distance between the ridges, and insulators between the spaces comprising the flat topped surfaces of the ridges processed to remove any residual conductors thereon.

13. The printed wiring board defined in claim 12 wherein the flat substrate surface and indented surfaces of the channels formed between said ridges is metallized over the channel surface area to define the conductors wider than the spacing between the ridges.

14. The printed wiring board defined in claim 12 with substantially U shaped channels metallized on the bottom and sidewalls thereby providing a substantially greater width of the conductor than would be disposed on a flat surface of the substrate in the same place.

15. The printed wiring board defined in claim 14 having a channel depth of about 0.006 in., a channel width of about 0.003 in., and a spacing between channels of about 0.003 in.

16. The printed wiring board of claim 15 with the metallized surface defining the conductor having a thickness of about 0.0014 in.

17. The printed wiring board of claim 14 with said ridges comprising a photopolymer material extending above a substantially flat insulating surface of a supporting body.

18. A printed wiring board assembly, comprising in combination, a solder mask layer disposed to partially cover a conductive circuit wiring pattern on a printed wiring board substrate, and a layer of conductive material visibly disposed to permanently adhere onto the outer surface of said solder mask layer comprising an indicia marking nomenclature pattern overlying a plurality of circuit wires on said wiring pattern produced by a dot matrix pattern of conductive material breaking up the indicia pattern area to reduce capacitive coupling between the conductor wires in said wiring pattern which are overlaid by the indicia pattern.

19. The method of producing a printed wiring board assembly having an insulation resist coating such as a solder mask layer disposed to extend upwardly from a conductive circuit wiring pattern on the printed wiring board substrate surface leaving exposed conductor pads at predetermined circuit contact positions on the substrate surface, comprising the steps of:

improving efficiency of circuit space usage with given board substrate dimensions thereby permitting additional circuit board patterns to be printed without increasing the substrate area by providing on the substrate surface a thin conductive circuit pattern, adhering to the substrate surface and insulation resist coating presenting a flush flat surface plateau with access channels downwardly extending thereinto the substrate surface, coating channel sidewalls with a thin conductive coating electrically contacting the exposed conductor pads, disposing on the surface of said insulation coating a layer of conductive material as indicia marking nomenclature in a pattern electronically coupled to the circuit board wiring pattern on the substrate surface, and disposing the conductive material in said indicia pattern in a dot matrix pattern to reduce capacitance coupling between conductor wires in said wiring pattern on the substrate surface.

20. The method of producing a printed wiring board assembly having an insulation resist coating such as a solder mask layer disposed to extend upwardly from a conductive circuit wiring pattern on the printed wiring board substrate surface leaving exposed conductor pads at predetermined circuit contact positions on the substrate surface, comprising the steps of:

improving efficiency of circuit space usage with given board substrate dimensions thereby permitting additional circuit board patterns to be printed without increasing the substrate area by providing on the substrate surface a thin conductive circuit pattern, adhering to the substrate surface an insulation resist coating presenting a flush flat surface plateau with access channels downwardly extending thereinto exposing conductor pads in the conductive circuit pattern on the substrate surface, coating channel sidewalls with a thin conductive coating electrically contacting the exposed conductor pads, disposing on the surface of said insulation coating a layer of conductive material as indicia marking nomenclature in a pattern electronically coupled to the circuit board wiring pattern on the substrate surface, and photoprinting a layer of liquid photopolymer overlying the printed wiring on said board to produce a permanently adhered said resist coating.

21. The method of claim 20 including the step of electrically connecting the layer of conductive material disposed on the surface of the insulation coating to the wiring pattern by means of said coating on the sidewalls.

22. The method of claim 21 including the step of forming in said pattern disposed on the surface of the insulation coating a contiguous enlarged pad conductor surface area in part disposed on the insulation resist coating surface.

23. The method of claim 20 including the step of forming in said pattern disposed on the surface of the insulation coating a set of test connector leads electrically connected to at least a portion of the circuit pad positions and leading to and forming connector terminals at the edge of the printed wiring board substrate.

24. The method of claim 23 including the steps of testing the printed wiring board by means of test equipment coupled to said connector terminals, and removing the set of connector test leads from the surface of the insulation coating after testing.

25. The method of claim 20 including the step of depositing the layer of conductive material on the flat flush plateau surface of the insulation coating.

26. The method of claim 25 including the steps of temporarily using the conductive pattern on the insulation coating surface for processing the manufacture and testing of the printed wiring board and removing that conductive pattern from the plateau surface.

27. The method of claim 20 including the step of covering in part the circuit pattern coating on the surface of the substrate with the resist coating surface.

28. The method of claim 20 including the steps of indenting the plateau surface of the resist insulation coating in a predetermined pattern, and disposing at least in part said pattern of conductive material disposed on the surface of the insulation coating in the indented pattern.

29. The method of claim 20 including the step of photoprinting said resist coating to overly portions of a printed wiring pattern on said board.

30. The method of claim 20 including the steps of photoprinting said resist coating with channels extending between the surface plateau and the substrate surface, and coating the substrate surface and channel sidewalls with a thin conductive layer to constitute at least a portion of the printed wiring pattern on said board.

31. The method of producing a printed wiring board assembly having an insulation resist coating such as a solder mask layer disposed to extend upwardly from a conductive circuit wiring pattern on the printed wiring board substrate surface leaving exposed conductor pads at predetermined circuit contact positions on the substrate surface, comprising the steps of:

improving efficiency of circuit space usage with given board substrate dimensions thereby permiting additional circuit board patterns to be printed without increasing the substrate area by providing on the substrate surface a thin conductive circuit pattern, adhering to the substrate surface an insulation resist coating presenting a flush flat surface plateau with access channels downwardly extending thereinto exposing conductor pads in the conductive circuit pattern on the subtrate surface, coating channel sidewalls with a thin conductive coating electrically contacting the exposed conductor pads, disposing on the surface of said insulation coating a layer of conductive material as indicia marking nomenclature in a pattern electronically coupled to the circuit board wiring pattern on the substrate surface, and providing at least one temporary conductive path on said insulation surface plateau with electrical connection to the circuit wiring pattern, conducting electrical current through said temporary conductive path to said circuit wiring pattern in a manufacturing step, and removing the temporary conductive path from the plateau following completion of said manufacturing step.

32. The method defined in claim 31 further including the manufacturing step of electro depositing conductive material on circuit wires in the wiring pattern by means of said electrical current.

33. The method defined in claim 31 further including the manufacturing step of passing electrical test signals to the circuit wiring pattern with said electrical current.

34. The method of claim 33 comprising the further step of producing an intermediate product, namely, a printed wiring board assembly having a test wiring pattern positioned on said plateau connected to predetermined test point in the circuit wiring pattern.

35. The method of manufacturing printed wiring boards comprising the steps of:

providing an insulation layer over a significant portion of a printed wiring pattern on a printed wiring board leaving exposed predetermined wiring positions and presenting an outer flush plateau surface to which a conductor material may be removably affixed,

providing at least one temporary conductive path affixed on said surface electrically connecting the temporary conductive path with a predetermined conductive position on the printed wiring pattern,

conducting electrical current through said temporary conductive path to said wiring pattern in a manufacturing step, and

removing the temporary conductive path from said surface following completion of said manufacturing step.

36. The method of claim 35 further including the step of electro depositing conductive material on the wiring positions in the wiring pattern exposed through the insulation layer with said electrical current.

37. The method of claim 35 including the step of passing electrical test signals to the circuit wiring pattern with said electrical current.