DC-AC inverter with overload driving capability

• US 4,706,177 A
• Filed: 11/14/1985
• Issued: 11/10/1987
• Est. Priority Date: 11/14/1985
• Status: Expired due to Fees

• Current Assignee: Elliot Josephson
• Original Assignee: Elliot Josephson
• Inventors: Josephson, Elliot
• Primary Examiner(s): Salce, Patrick R.
• Assistant Examiner(s): Jones, Judson H.
• Application Number:
  US06/797,834
• Time in Patent Office: 726 Days
• Field of Search: 363/17, 363/24, 363/25, 363/26, 363/37, 363/40, 363/41, 363/50, 363/56, 363/97, 363/98, 363/132, 363/133, 363/134, 361/87, 323/272, 323/907
• US Class Current: 363/24
• CPC Class Codes: H02H 7/1227 responsive to abnormalities in the output circuit, e.g. short circuit
• CPC Class Codes: H02M 1/007 Plural converter units in cascade push-pull DC/DC converters with pre-regulator H02M3/3374; DC-AC converters following a DC-DC stage including a high frequency transformer H02M7/4807; DC-AC converters following a DC-DC conversion stage generating periodically varying voltages H02M7/4826
• CPC Class Codes: H02M 3/33569 having several active switching elements H02M3/3353 takes precedence
• CPC Class Codes: H02M 7/4807 having a high frequency intermediate AC stage
• CPC Class Codes: H02M 7/5381 Parallel type

Abstract

A DC-AC inverter includes a bridge converter for converting an input DC into an output AC signal which uses field-effect transistors in the bridge circuit. The characteristics of the field-effect transistors enable the bridge converter to temporarily supply power in significant overload conditions. A DC-DC converter may also be included between the DC power source and the bridge converter to provide voltage boosting, when required. Field-effect transistors are also included in the DC-DC converter for power switching. The duration and amount of overload current output by the bridge converter is monitored and when an overcurrent condition beyond a predetermined amount or duration is detected, the bridge converter is disabled. The bridge converter is reenabled at a predetermined time thereafter.

A plurality of field effect transistors may be connected in parallel at each location wherein a solid state power switching device is used in the inverter to thereby multiply the power handling capacity of the inverter as a whole.

Claims

1. An inverter circuit for converting a low voltage DC source into a higher voltage output AC source generated between first and second AC output terminals, comprising:

means for converting said low voltage DC source into a higher second DC voltage source including a positive node and a negative return node;

bridge converter means including first, second, third and fourth field-effect transistors for converting said second DC voltage source into an output AC source, each of said first, second, third and fourth field-effect transistors including gate, source and drain terminals, the drain of said first transistor connected to said positive node, said source of said first transistor connected to said first output AC terminaI and to said drain of said second field-effect transistor, the source of said second field-effect transistor connected to said negative return node, the drain of said third field-effect transistor connected to said positive node, the source of said third field-effect transistor connected to said second AC output terminal and to the drain of said fourth field-effect transistor, and a source of said fourth field-effect transistor connected to said negative return node, said bridge converter means further comprising means for driving said first, second, third and fourth field-effect transistor for periodically translating said transistors between their conducting and non-conducting states, said driving means comprising;

first, second, third and fourth driver switches;

a first transformer having first, second, third and fourth windings, said first winding connected between the gate of said first field-effect transistor and the source of said first field-effect transistor, said third winding connected between the gate and source of said second field-effect transistor, said second winding connected to said first driver switch and said fourth winding connected to said second driver switch;

a second transformer having first, second, third and fourth windings, said first winding connected between the gate and source of said third field-effect transistor, said third winding connected between the gate and source of said fourth field-effect transistor, said second winding connected to said third driver switch and said source winding connected to said fourth driver switch;

such that when a respective first, second, third or fourth driver switch means turns on, current is caused to flow through its associated said winding so as to create a voltage drop in a respective winding connected to a field effect transistor gate sufficient to cause said field-effect transistor to switch from a non-conducting to a conducting state; and

control means for providing control signals to said first, second, third and fourth driver switches in a predetermined sequence such that a quasi-square wave is generated across said AC output terminals; and

means for detecting an AC output overcurrent condition and for disabling said bridge converter means as a predetermined function of the amplitude and time duration of said overcurrent condition.

2. The inverter of claim 1 wherein said control means comprises a first flip-flop whose output states control the state of said first and second driver switches respectively;

a second flip-flop whose output states control the state of said third and fourth driver switches; and

a clock for generating alternating pulses for periodically changing the state of said first flip-flop and said second flip-flop, including means for regulating the time at which said flip-flops change state as a function of the current level of said second DC source voltage.

6. The inverter circuit of claim 1 wherein said means for detecting an AC output overcurrent condition and for disabling said bridge converter means further comprises means for reducing the amount of amplitude of said overload condition required to disable said bridge converter means as a function of increasing temperature.

3. An inverter circuit for converting a low voltage DC source into a higher voltage output AC source generated between first and second AC output terminals, comprising:

means for converting said low voltage DC source into a higher second DC voltage source including a positive node and a negative return node;

bridge converter means including first, second, third and fourth field-effect transistors for converting said second DC voltage source into an output AC source, each of said first, second, third and fourth field-effect transistors including gate, source and drain terminals, the drain of said first transistor connected to said positive node, said source of said first transistor connected to said first output AC terminal and to said drain of said second field-effect transistor, the source of said second field-effect transistor connected to said negative return node, the drain of said third field-effect transistor connected to said positive node, the source of said third field-effect transistor connected to said second AC output terminal and to the drain of said fourth field-effect transistor, and the source of said fourth field-effect transistor connected to said negative return node, and wherein each of said first, second, third and fourth field-effect transistor comprise at least two field-effect transistor connected in parallel; and

means for detecting an AC output overcurrent condition and for disabling said bridge converter means as a predetermined function of the amplitude and time duration of said overcurrent condition.

4. The inverter circuit of claim 3 wherein said means for detecting an AC output overcurrent condition and for disabling said bridge converter means further comprises means for reducing the amount of amplitude of said overload condition required to disable said bridge converter means as a function of increasing temperature.

5. The inverter of claim 4 wherein said means for reducing the amount of overload comprises a negative temperature coefficient resistor.