Retry mechanism for releasing control of a communications path in digital computer system

• US 4,706,190 A
• Filed: 07/16/1985
• Issued: 11/10/1987
• Est. Priority Date: 09/22/1983
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Bomba, Frank C., Jenkins, Stephen R.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Ure, Michael J.
• Application Number:
  US06/755,952
• Time in Patent Office: 847 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/108
• CPC Class Codes: G06F 13/4213 with asynchronous protocol

Abstract

When a device on a computer communications bus receives a request to enter into a transaction and is not yet ready to perform the transaction, it sends a retry signal to the requesting device to indicate to it that it should terminate the transaction that it has initiated. If the responding device may later be ready to engage in the transaction if the transaction is initiated again some time in the future, the signal is a retry signal and differs from the signal that the requesting device would receive if the transaction were to be terminated for some other reason. As a result, the master device can be arranged to re-initiate only those transactions for which there is a likelihood that they can be carried out to completion when they are attempted again.

Claims

1. For connection to a common communications path in a data processing system, which path carries data signals that represent data being read or written, the path including address lines for carrying signals that designate memory location from which data are to be read, command lines for carrying commands, including interlock-read commands that request that data be read from a memory location designated by the address signals and unlock-write commands that request that data be written into a memory location designated by the address signals, and response lines for carrying one of at least three response signals, namely, an acknowledgement signal, a no-acknowledgement signal that results when no device places signals on the response lines, and a retry signal, a memory device comprising:

A. acknowledgement means including at least one interlock-bit register, each interlock-bit register being associated with at least one address, being arranged selectively to assume one of a retry-enabled state and a retry-disabled state, and, when the memory device is connected to the common communications path, being responsive to address signals representing the address associated therewith to;

(i) assume its retry-enabled state when it receives an interlock-read command and it is in its retry-disabled state; and

(ii) assume its retry-disabled state when it receives an unlock-write command and it is in its retry-enabled state,

said acknowledgement means responding to the presence on the common communications path of an interlock-read command and an address associated with any included interlock-bit register thereof to;

(i) place retry signals on the common communications path when the interlock-bit register associated with the address signals on the common communications path is in its retry-enabled state; and

(ii) place acknowledgement signals on the common communications path when the interlock-bit register associated with the address signals on the common communications path is in its retry-disabled state; and

B. a plurality of memory locations for containing data, each memory location associated with an address and, when the memory device is connected to the common communications path;

(i) being responsive to the presence on the common communications path of the address associated therewith, to an interlock-read command, and to the state of the interlock bit associated with the address of that memory location to place on the common communications path data signals representing the data stored in that location if the interlock-bit register associated with the address of that location is in its retry-disabled state and to refrain from placing on the common communications path via signals representing the data stored in that location if the interlock-bit register associated with the address of that location is in its retry-enabled state, and

(ii) further being responsive to its address on the common communications path and to an unlock-write command to store therein data represented by data signals carried by the common communications path.

2. For connection to a common communications path in a data processing system, which path includes lines for carrying commands that specify a transaction to be performed, for carrying stall signals that request extension of the length of the transaction, for carrying no-acknowledgement signals that cause termination of the transaction in one way, and for carrying retry signals that cause termination of the transaction in another way, a slave device comprising:

A. transaction means responsive to a command from a master device on the common communications path for performing a transaction with the master device that has placed the command on the path when the slave device is connected to the common communications path;

B. stall means responsive to the transaction means for placing a stall signal on the communications path during the device'"'"'s performance of the transaction specified by the command signal when the slave device is connected to the common communications path if the time required by the transaction means to complete a step of that transaction is more than an allotted period of time; and

C. retry means for monitoring the stall means to keep track of how long the device has asserted the stall signal and for placing the retry signal on the common communications path when the device has asserted the stall signal for more than a predetermined maximum time.

3. A data processing system comprising:

A. a common communications path;

B. at least one master device including;

i. means for (a) initiating at least some read transactions by placing on the common communications path address signals to designate a memory location from which data are to be read and interlock-read commands to request that data be read from a memory location designated by the address signals and (b) initiating at least some write transactions by placing on the common communications path address signals to designate a memory location in which data are to be written, placing on the common communications path data to be stored, and placing on the common communications path unlock-write commands that request that the data placed on the common communications path be stored in the addressed location;

ii. means for monitoring the common communications path, after the initiating means initiates a read transaction, for one of at least three response signals, namely, an acknowledgement signal, a no-acknowledgement signal, and a retry signal;

iii. means for completing the read transaction in response to the acknowledgement signal;

iv. means for terminating the transaction in one manner in response to the no-acknowledgement signal; and

v. means for terminating the transaction in a different manner in response to the retry signal; and

C. a memory device comprising;

i. acknowledgement means including at least one interlock-bit register, each interlock-bit register being associated with at least one address and being arranged selectively to assume one of a retry-enabled state and a retry-disabled state and being responsive to address signals representing the address associated therewith to (a) assume its retry-enabled state when it receives an interlock-read command in its retry-disabled state and (b) assume its retry-disabled state when it receives an unlock-write command and it is in its retry-enabled state, said acknowledgement means responding to the presence on the common communications path of an interlock-read command and an address associated with any included interlock-bit register thereof to (a) place retry signals on the common communications path when the interlock-bit register associated with the address signals on the common communications path is in its retry-enabled state, and (b) place acknowledgement signals on the common communications path when the interlock-bit register associated with the address signals on the common oommunications path is in its retry-enabled state; and

ii. a plurality of memory locations for containing data, each memory location being associated with an address, being responsive to its address on the common communications path, to an interlock-read command, and to the state of the interlock bit associated with the address of that memory location to place on the common communications path data signals representing the data stored in that location if the state of the interlock-bit register associated with its address is in its retry-disabled state and to refrain from placing on the common communications path data signals representing the data stored in that location if the state of the interlock-bit register associated with its address is in its retry-enabled state, each memory location further being responsive to its address on the common communications path and to an unlock-write command to store therein data represented by data signals placed on the common communications path by a master device.

4. A data processing system comprising:

A. a common communication path;

B. at least one master device connected to the common communications path and including;

i. means for initiating a transaction by placing a command on the common communications path;

ii. means for performing the transaction for a predetermined transaction time associated with that transaction;

iii. means for extending the transaction time in response to the presence of a predetermined stall signal on the common communications path;

iv. means for terminating the transaction in one way in response to the presence of a no-acknowledgement signal on the common communications path, and

v. means for terminating the transaction in another way in response to the presence of a retry signal on the common communications path; and

C. a slave device comprising;

i. transaction means responsive to a command from a master device on the common communications path for performing a transaction with the master device that has placed the command on the path;

ii. stall means responsive to the transaction means for placing a stall signal on the communications path during the device'"'"'s performance of the transaction specified by the command signal if the time required by the transaction means to complete a step of that transaction is more than an allotted period of time; and

iii. retry means for monitoring the stall means to keep track of how long the device has asserted the stall signal and for placing the retry signal on the common communications path when the device has asserted the stall signal for more than a predetermined maximum time.