Configurable logic element

• US 4,706,216 A
• Filed: 02/27/1985
• Issued: 11/10/1987
• Est. Priority Date: 02/27/1985
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Carter, William S.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/706,429
• Time in Patent Office: 986 Days
• Field of Search: 365/94, 365/103, 365/154, 365/189, 365/230
• US Class Current: 365/94
• CPC Class Codes: G11C 19/282 with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
• CPC Class Codes: H03K 19/1733 Controllable logic circuits H03K19/177 takes precedence
• CPC Class Codes: H03K 19/1736 in which the wiring can be modified
• CPC Class Codes: H03K 3/037 Bistable circuits
• CPC Class Codes: H03K 5/1534 Transition or edge detectors

Abstract

A configurable logic circuit achieves versatility by including a configurable combinational logic element, a configurable storage circuit, and a configurable output select logic. The input signals to the configurable combinational logic element are input signals to the configurable logic circuit and feedback signals from the storage circuit. The storage circuit may be configured to operate as a D flip flop with or without set and reset inputs, an RS latch, a transparent latch with or without set and reset inputs, or as an edge detector. In conjunction with the combinational logic element, the storage circuit may also operate as a stage of a shift register or counter. The output select logic selects output signals from among the output signals of the combinational logic element and the storage circuit.

Claims

1. A configurable logic element comprising:

means for receiving a first plurality of N binary input signals;

means for receiving a second plurality of M binary feedback signals;

means for selecting K of said M+N binary signals (where K≦

N+M);

combinational logic means for receiving said K binary signals from said means for selecting, said combinational logic means having a plurality of configurations including at least

a first configuration in which said combinational logic means generates a first set of binary output signals, each of which represents a function of some of said K binary signals and

a second configuration in which said configurable combinational logic means generates a second set of binary output signals, each of which represents a function of some of said K binary signals, wherein the set of functions represented by said first set of binary signals is not the same as the set of functions represented by said second set of binary signals;

a configurable storage circuit comprising;

a plurality of input leads for receiving a plurality of input signals, said input signals corresponding to said input leads on a one-to-one basis, said input signals comprising selected ones of said binary output signals of said combinational logic means and selected ones of said N binary input signals,

memory means for storing data, said memory means having at least a first and a second input lead and at least one output lead;

first means having a first configuration in which said first means provides a first selected one of said input signals of said configurable storage circuit to said first input lead of said memory means

second means having a first and a second configuration in which said second means provides a second and a third selected one, respectively of said input signals of said configurable storage circuit to said second input lead of said memory means,

said memory means generating said second plurality of M binary signals in response to said signals provided by said first and said second means; and

a configurable select logic comprising;

means for receiving said output signals generated by said combinational logic means and said M binary signals generated by said configurable storage circuit, and

means for selecting output signals from among the signals received by said select logic.

2. A configurable logic element as in claim 1 wherein said second means of said configurable storage circuit has a third configuration in which said second means provides the complement of said second selected one of said input signals to said second input lead of said memory means.

9. A configurable logic element as in claim 1, 2, 6, 7, or 8 wherein said second means of said configurable storage circuit includes means for generating a first constant signal and has a fourth configuration in which said second means provides said first constant signal to said second lead.

10. A configurable logic element as in claim 9 wherein said first means of said configurable storage circuit includes means for generating a second constant signal and means for generating a third constant signal and wherein said first means has a second and a third configuration in which it provides said second and said third constant signal, respectively, to said first input lead

11. A configurable logic element as in claim 10 wherein said first input lead of said memory of said configurable storage circuit is a data input lead, said second input lead of said memory means of said configurable storage circuit is a clock input lead, and wherein said memory means further comprises a set and a reset input lead.

3. A configurable logic element comprising:

means for receiving a first plurality of N binary input signals;

means for receiving a second plurality of M binary feedback signals;

means for selecting K of said M+N binary signals of said first and said second plurality (where K≦

N+M);

configurable combinational logic means comprising

first configurable means for receiving said K binary input signals, said first configurable means having at least a first configuration in which said first configurable means generates a first set of output signals said first set being a first subset of said K input signals, and a second configuration in which said first configurable means generates a second set of output signals said second set being a second subset of said K input signals, wherein said first set is not equal to said second set;

first memory means having a plurality of storage locations, each of said storage locations for storing a binary bit;

first location selection means for receiving said output signals of said first configurable means and for selecting a storage location within said first memory means in response to said output signals of said first configurable means and for providing a first output signal representing the binary bit stored in said selected storage location within said first memory;

a configurable storage circuit comprising;

a plurality of input leads for receiving a plurality of input signals said input signals corresponding to said input leads on a one-to-one basis, said input signals comprising selected ones of said output signals of said first location selection means and selected ones of said N binary input signals,

memory means for storing data, said memory means having at least a first and a second input lead and at least one output lead;

first means having a first configuration in which said first means provides a first selected one of said input signals of said configurable storage circuit to said first input lead of said memory means;

second means having a first and a second configuration in which said second means provides a second and a third selected one, respectively, of said input signals of said configurable storage circuit to said second input lead of said memory means,

said memory means generating said second plurality of M binary signals in response to said signals provided by said first and said second means; and

a configurable select logic comprising;

means for receiving the output signals produced by said first location selection means of said combinational logic and said M binary signals; and

means for selecting output signals from among the signals received by said select logic.

4. A configurable logic element as in claim 3 wherein said configurable combinational logic means further comprises:

second configurable means for receiving said K binary input signals, said second configurable means having at least a first configuration in which said second configurable means generates a third set of output signals, said third set being a third subset of said K input signals, and a second configuration in which said second configurable means generates a fourth set of output signals, said fourth set being a fourth subset of said K input signals wherein said third set is not equal to said fourth set;

second memory means having plurality of storage locations, each of said storage locations for storing a binary bit;

second location selection means for receiving said output signals of said second configurable means and for selecting a storage location within said second memory means in response to said output signals of said second configurable means, said second location selection means providing a second output signal representing the data bit stored in said selected storage location within said second memory;

steering logic means for receiving said first and said second output signals of said first and said second location selection means, said steering logic means having a first configuration in which said steering logic means provides a first output signal equal to said first output signal of said first location selection means and a second output signal equal to said second output signal of said second location selection means, said steering logic means having a second configuration in which said steering logic means provides an output signal equal to a selected one of said first and said second output signals of said first and said second location selection means,

wherein said input signals of said configurable storage circuit further comprise selected ones of said output signals of said steering logic means

and wherein said means for receiving the output signals in said configurable select logic receives said output signals of said steering logic means.

5. A configurable logic element as in claim 4 wherein said second means of said configurable storage circuit has a third configuration in which said second means provides the complement of said second selected one of said input signals to said second input lead of said memory means

6. A configurable logic element as in claim 4 wherein the number of signals in each of said first, said second, said third and said fourth sets of output signals of said first and second configurable means of said configurable combinational logic means is L where L is a selected positive integer less than or equal to K.

7. A configurable logic element as in claim 6 wherein L=K-1.

8. A configurable logic element as in claim 7 wherein said first memory means comprises 2^K- 1 storage locations, each of said storage locations being capable of being programmed and reprogrammed and wherein said second memory means comprises 2^K- 1 storage locations, each of said storage locations being capable of being programmed and reprogrammed.

12. A configurable combinational logic circuit comprising:

first configurable means for receiving K binary input signals, said first configurable means having at least a first configuration in which said first configurable means generates a first set of output signals said first set being a first subset of said K input signals, and a second configuration in which said first configurable means generates a second set of output signals said second set being a second subset of said K input signals wherein said first set is not equal to said second set;

first memory means having a plurality of storage locations, each of said storage locations for storing a binary bit;

first location selection means for receiving said output signals of said first configurable means and for selecting a storage location within said first memory means in response to said output signals of said first configurable means and for providing a first output signal representing the binary bit stored in said selected storage location within said first memory.

13. A configurable combinational logic circuit as in claim 12 further including:

second configurable means for receiving said K binary input signals, said second configurable means having at least a first configuration in which said second configurable means generates a third set of output signals, said third set being a third subset of said K input signals, and a second configuration in which said second configurable means generates a fourth set of output signals, said fourth set being a fourth subset of said K input signals, wherein said third set is not equal to said fourth set;

second memory means having a plurality of storage locations, each of said storage locations for storing a binary bit;

second location selection means for receiving said output signals of said second configurable means and for selecting a storage location within said second memory means in response to said output signals of said second configurable means, said second location selection means providing a second output signal representing the data bit stored in said selected storage location within said second memory; and

steering logic means for receiving said first and said second output signals of said first and said second location selection means, said steering logic means having a first configuration in which said steering logic means provides a first output signal equal to said first output signal of said first location selection means and a second output signal equal to said second output signal of said second location selection means, said steering logic means having a second configuration in which said steering logic means provides an output signal equal to a selected one of said first and said second output signals of said first and said second location selection means.

14. A configurable logic element as in claim 13 wherein the number of signals in each of said first, said second, said third and said fourth sets of output signals is L where L is a selected positive integer less than or equal to K.

15. A configurable logic circuit as in claim 14 wherein L=K-1.

16. A configurable logic element as in claim 15 wherein said first memory means comprises 2^K-1 storage locations, each of said storage locations being capable of being programmed and reprogrammed and wherein said second memory means comprises 2^K- 1 storage locations, each of said storage locations being capable of being programmed and reprogrammed.

17. A configurable storage circuit comprising:

memory means for storing data said memory means having at least a first and a second input lead;

a first set of one or more input leads corresponding to said first input lead each input lead of said first set for receiving a corresponding input signal;

a second set of one or more input leads corresponding to said second input lead, each input lead of said second set for receiving a corresponding input signal;

first means which, for each given lead in said first set, has a corresponding configuration in which said first means provides the input signal on said given lead to said first input lead;

second means which, for each given lead in said second set, has a corresponding first configuration in which said second means provides the input signal on said given lead to said second lead;

said memory means generating one or more output signals in response to said signals provided by said first means and said second means.

18. A configurable storage circuit as in claim 17 wherein said second means, for some given lead in said second set, has a corresponding second configuration for providing the complement of the signal on said some given lead to said second lead.

19. A configurable storage circuit as in claim 17 wherein said second means includes means for generating a first constant signal and has a configuration in which said second means provides said first constant signal to said second lead.

20. A configurable storage circuit as in claim 19 wherein said first means includes means for generating a second constant signal and means for generating a third constant signal and wherein said first means has a first and a second additional configuration in which it provides said second and said third constant signals, respectively, to said first input lead.

21. A configurable logic element comprising:

means for receiving a first plurality of N binary input signals;

means for receiving a second plurality of M binary feedback signals;

means for selecting K of said M+N binary signals (where K≦

N+M);

combinational logic means for receiving said K binary signals from said means for selecting, said configurable combinational logic means having a plurality of configurations for generating binary output signals;

a configurable storage circuit for receiving selected ones of said binary output signals of said configurable combinational logic means and selected ones of said N binary input signals and for generating said M binary feedback signals said configurable storage circuit having a plurality of configurations; and

a configurable select logic comprising means for receiving said output signals generated by said combinational logic means and said M binary signals generated by said configurable storage circuit and means for selecting output signals from among the signals received by said select logic.