Data processor control unit having an interrupt service using instruction prefetch redirection

• US 4,709,324 A
• Filed: 11/27/1985
• Issued: 11/24/1987
• Est. Priority Date: 11/27/1985
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Kloker, Kevin L.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/802,491
• Time in Patent Office: 727 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 712/207
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

A data processor control unit which provides instructions for execution by a data processor and minimizes instruction cycles lost as overhead. A pipelined instruction stream is used in which instruction addresses are selectively coupled from a program counter and a prefetch counter to a program memory which provides actual instructions. The instructions are stored in a prefetched register, decoded and then loaded into an instruction register coupled to the data processor. When an interrupt service request is made by a device peripheral to the processor, the prefetch instruction address flow is immediately redirected and a predetermined number of interrupt instruction words are prefetched by an interrupt address generator before completion of execution of normal program instructions has occurred. Therefore, interrupt instructions are fetched and jammed into a pipelined instruction stream regardless of instruction cycle boundaries. Similarly, prefetch instruction address flow is redirected back to normal instruction words before completion of the decoding and execution of interrupt service instructions so that substantially no instruction execution cycles of the data processor are lost as overhead.

Claims

1. In a data processing system having a data processor for executing intructions and a control unit for providing said instructions to the data processor, said control unit selectively providing prefetched normal instructions in an absence of an interrupt request from a peripheral device and providing prefetched interrupt instructions in response to an interrupt request, a method for minimizing instruction cycles in which no instructions are being executed by the data processor associated with interrupting instruction flow to execute an interrupt service routine in response to an interrupt request, comprising the steps of:

detecting receipt of a request from the peripheral device to interrupt normal instruction flow from the control unit to the data processor;

providing a control signal for a duration of at least one instruction cycle in response to the request to interrupt normal instruction flow;

redirecting normal instruction prefetches for the at least one instruction cycle in response to the control signal to provide at least one interrupt instruction prefetch, said at least one interrupt instruction prefetch being initiated before said prefetched normal instructions complete execution;

redirecting said at least one interrupt instruction prefetch immediately after the at least one instruction cycle duration of the control signal to continue providing normal instruction prefetches, said normal instruction prefetches being initiated before said at least one prefetched interrupt instruction completes execution.

2. The method of claim 1 further comprising the step of:

initiating said at least one interrupt instruction prefetch before decoding whether a most recently prefetched normal instruction is a multiple word instruction which is not completely prefetched.

3. The method of claim 1 further comprising the step of:

initiating said normal instruction prefetches before decoding whether a most recently prefetched interrupt instruction is a multiple word instruction which is not completely prefetched.

4. In a data processing system having a data processor for executing instructions and a control unit for providing the instructions to the data procesor, said control unit prefetching instructions by providing instruction addresses which address instructions to be executed via a program address bus, providing instructions to a program data bus in response to the instruction addresses and decoding the instructions, a method for minimizing overhead associated with interrupting instruction flow to the data processor in response to a request from a peripheral device for interrupt service from the data processor, comprising the steps of:

detecting receipt of a request from the peripheral device to interrupt normal instruction flow from the control unit to the data processor;

providing a control signal for a predetermined time period during one or more instruction cycles in response to the request to interrupt normal instruction flow;

redirecting flow of the prefetching of normal instructions in response to the control signal by providing at least one predetermined interrupt instruction address to the program address bus before completion of the currently executing instruction, if any;

prefetching and decoding at least one interrupt instruction in response to at least one interrupt instruction address; and

redirecting flow of the prefetching of interrupt instructions by continuing to provide normal instruction addresses to the program address bus immediately after the predetermined time period the control signal is provided and before completion of the decoding and executing of the at least one interrupt instruction, there by minimizing instruction cycles in which no instructions are being executed by the data processor.

5. A data processor control unit for providing prefetched normal instructions for execution by a data processor which can be interrupted by an interrupt request signal to provide at least one prefetched interrupt instruction while minimizing instruction execution cycles lost as overhead during an interrupt, comprising:

a program address bus for communicating normal instruction addresses and interrupt instruction addresses;

program address storage means coupled to the program address bus for selectively receiving, storing and providing normal instruction addresses;

prefetch address storage means coupled to the program address bus for selectively storing and providing normal instruction addresses;

incrementer means having an input coupled to the program address bus and an output coupled to the prefetch address storage means, for selectively incrementing instruction addresses stored by the prefetch address storage means to a successive instruction address;

interrupt control means for providing an interrupt fetch control signal in response to detecting the interrupt request signal and before said normal instructions complete execution and before decoding whether a most recently prefetched normal instruction is a multiple word instruction which is not completely prefetched, said interrupt fetch control signal controlling when a predetermined interrupt address or addresses of a plurality of interrupt addresses is provided to the program address bus;

interrupt address means coupled to both the program address bus and interrupt control means for selectively providing a predetermined interrupt address or addresses of a plurality of the interrupt addresses to the program address bus in response to both the interrupt request signal and the interrupt fetch signal;

program memory means having an input coupled to the program address bus and an output for providing prefetched normal instructions and prefetched interrupt instructions in response to normal instruction addresses and interrupt instruction addresses, respectively;

first instruction storage means having an input coupled to the program memory means and the interrupt control means, for selectively receiving, storing and providing instructions and providing an interrupt acknowledge signal indicating that an interrupt instruction is stored;

instruction decoding means having a first input coupled to the first instruction storage means for receiving the interrupt ackowledge signal, a second input coupled to the first instruction storage means for selectively receiving an instruction, and an output for selectively providing decoded instructions; and

second instruction storage means having a first input coupled to the output of the instruction decoding means, a second input for receiving the interrupt acknowledge signal, and an output for selectively providing decoded instructions to the data processor.

6. The data processor control unit of claim 5 wherein said second instruction storage means has a second output coupled to a control input of said program address storage means for selectively maintaining the contents of the program address storage means constant.