Semiconductor memory

• US 4,709,353 A
• Filed: 12/15/1986
• Issued: 11/24/1987
• Est. Priority Date: 05/13/1981
• Status: Expired due to Term

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Hitachi, Ltd.
• Inventors: Kawamoto, Hiroshi, Shimohigashi, Katsuhiro, Masuda, Hiroo, Ikuzaki, Kunihiko
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/941,840
• Time in Patent Office: 344 Days
• Field of Search: 365/149, 365/182, 365/184, 365/185, 365/186, 365/190, 365/205, 365/203
• US Class Current: 365/205
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the data lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

Claims

1. A semiconductor memory formed in a semiconductor integrated circuit comprising:

a pair of data lines which are formed substantially in parallel to each other;

a plurality of word lines, each of which is arranged so as to intersect with both of said pair of data lines;

a plurality of memory cells, each of which is coupled to one of said word lines and to one of said data lines, and each of which includes a MOS transistor of a first conductivity type and a capacitor;

selecting means coupled to said plurality of word lines for selecting one from said plurality of memory cells;

amplifier means coupled to said pair of data lines for amplifying a difference which appears between said data lines in response to selection of one from said memory cells by said selecting means, wherein said amplifier means includes a pair of first MOS transistors of the first conductivity type and a pair of second MOS transistors of a second conductivity type, wherein each transistor of said pair of first MOS transistors has its gate cross-coupled to the drain of the other transistor of said pair of first MOS transistors, wherein the drain of one of said pair of first MOS transistors is coupled to one of said pair of data lines and the drain of the other of said pair of first MOS transistors is coupled to the other of said pair of data lines, wherein each transistor of said pair of second MOS transistors has its gate cross-coupled to the drain of the other transistor of said pair of second MOS transistors, wherein the drain of one of said pair of second MOS transistors is coupled to one of said pair of data lines and the drain of the other of said pair of second MOS transistors is coupled to the other of said pair of data lines; and

precharging means for setting said data lines at a predetermined level between levels on said data lines obtained by operating of said amplifier means after said selecting means makes said memory cells non-selecting state.

2. A semiconductor memory formed in a semiconductor integrated circuit comprising:

a pair of data lines disposed substantially parallel and adjacent to each other;

a plurality of word lines, each of which is arranged so as to intersect with both of said pair of data lines;

a plurality of memory cells, each of which is coupled to one of said word lines and one of said pair of data lines at a cross point thereof, each memory cell having an address terminal connected to a corresponding word line so that each word line is connected to the address terminal of only one memory cell, and having a data terminal connected to a corresponding data line;

said each memory cell including a MISFET having a gate electrode connected to said address terminal, a first electrode connected to said data terminal and a second electrode connected to a capacitor;

selecting means coupled to said plurality of word lines for selecting one from said plurality of memory cells;

amplifier means coupled to said pair of data lines for amplifying a potential difference which appears between said data lines in response to selection of one from said plurality of memory cells by said selecting means, wherein said amplifier means includes a pair of first MISFETs of a first conductivity type and a pair of second MISFETs of a second conductivity type, wherein each MISFET of said pair of first MISFETs has its gate cross-coupled to the drain of the other MISFET of said pair of first MISFETs, wherein the drain of one of said pair of first MISFETs is coupled to one of said pair of data lines and the drain of the other of said pair of first MISFETs is coupled to the other of said pair of data lines, wherein each MISFET of said pair of second MISFETs has its gate cross-coupled to the drain of the other MISFET of said pair of second MISFETs, wherein the drain of one of said pair of second MISFETs is coupled to one of said pair of data lines and the drain of the other of said pair of second MISFETs is coupled to the other of said pair of data lines; and

precharging means for setting said data lines at a potential intermediate between potantials on said data lines to be obtained by operating said amplifier means after said selecting means operates to place said plurality of memory cells in a non-selected state.

3. A semiconductor memory according to claim 2, further comprising control means for controlling the operation of said amplifier means, said control means including first switching means coupled between the source of each of said first MISFETs and a first potential terminal and second switching means coupled between the source of each of said second MISFETs and a second potential terminal.

4. A semiconductor memory according to claim 3, wherein said intermediate potential corresponds to a potential intermediate between binary signal levels to be stored in the memory cell.

5. A semiconductor memory according to claim 2, wherein said precharging means includes a third MISFET having a gate electrode for receiving a control signal, a first electrode coupled to one of said pair of data lines and a second electrode coupled to the other of said pair of data lines, said third MISFET controlled by said control signal so that said pair of data lines are electrically coupled to each other after said selecting means operates to place said plurality of memory cells in a non-selected state.

35. A semiconductor memory according to claim 4, wherein said precharging means includes a third MISFET having a gate electrode for receiving a control signal, a first electrode coupled to one of said pair of data lines and a second electrode coupled to the other of said pair of data lines, said third MISFET controlled by said control signal so that said pair of data lines are electrically coupled to each other after said selecting means operates to place said plurality of memory cells in a non-selected state.

6. A semiconductor memory formed in a semiconductor integrated circuit comprising:

a pair of data lines disposed substantially parallel and adjacent to each other;

a plurality of word lines, each of which is arranged so as to intersect with both of said pair of data lines;

a plurality of memory cells, each of which is coupled to one of said word lines and one of said pair of data lines at a cross point thereof, each memory cell having an address terminal connected to a corresponding word line so that each word line is connected to the address terminal of only one memory cell, and having a data terminal connected to a corresponding data line;

said each memory cell including a MISFET having a gate electrode connected to said address terminal, a first electrode connected to said data terminal and a second electrode connected to a capacitor;

selecting means coupled to said plurality of word lines for selecting one from said plurality of memory cells;

amplifier means coupled to said pair of data lines for amplifying a potential difference which appears between said data lines in response to selection of one from said plurality of memory cells by said selecting means, wherein said amplifier means includes a pair of first MISFETs of a first conductivity type and a pair of second MISFETs of a second conductivity type, wherein each MISFET of said pair of first MISFETs has its gate cross-coupled to the drain of the other MISFET of said pair of said MISFETs, wherein the drain of one of said pair of first MISFETs is coupled to one of said pair of data lines and the drain of the other of said pair of first MISFETs is coupled to the other of said pair of data lines, wherein each MISFET of said pair of second MISFETs has its gate cross-coupled to the drain of the other MISFET of said pair of second MISFETs, wherein the drain of one of said pair of second MISFETs is coupled to one of said pair of data lines and the drain of the other of said pair of second MISFETs is coupled to the other of said pair of data lines; and

precharging means responsive to a control signal for setting said data lines at a potential intermediate between potentials on said data lines to be obtained by operating said amplifier means, after said selecting means operates to place said plurality of memory cells into a non-selected state, wherein said precharging means includes a potential terminal for receiving a potential corresponding to said intermediate potential, a third MISFET having a gate electrode for receiving said control signal, a first electrode coupled to one of said pair of data lines and a second electrode coupled to said potential terminal, and a fourth MISFET having a gate electrode for receiving said control signal, a first electrode coupled to the other of said pair of data lines and a second electrode coupled to said potential terminal, said third and fourth MISFETs being controlled by said control signal so that said potential is provided to said data lines via said third and fourth MISFETs, respectively, after said selecting means operates to place said memory cells in a non-selected state.

7. A semiconductor memory according to claim 6, further comprising control means for controlling the operation of said amplifier means, said control means including first switching means coupled between the source of each of said first MISFETs and a first potential terminal and second switching means coupled between the source of each of said second MISFETs and a second potential terminal.

8. A semiconductor memory according to claim 7, wherein said intermediate potential corresponds to a potential intermediate between binary signal levels to be stored in the memory cell.

9. A semiconductor memory according to claim 8, wherein said precharging means includes a fifth MISFET having a gate electrode for receiving said control signal, a first electrode coupled to one of said pair of data lines and a second electrode coupled to the other of said pair of data lines, said fifth MISFET being controlled by said control signal so that said pair of data lines are electrically coupled to each other after said selecting means operates to place said memory cells into a non-selected state.

10. A semiconductor memory formed in a semiconductor integrated circuit comprising:

a pair of data lines disposed substantially parallel and adjacent to each other;

a plurality of word lines, each of which is arranged so as to intersect with both of said pair of data lines;

a plurality of memory cells, each of which is coupled to one of said word lines and one of said pair of data lines at a cross point thereof, each memory cell having an address terminal connected to a corresponding word line so that each word line is connected to the address terminal of only one memory cell, and having a data terminal connected to a corresponding data line;

said each memory cell including a MISFET having a gate electrode connected to said address terminal, a first electrode connected to said data terminal and a second electrode connected to a capacitor;

selecting means coupled to said plurality of word lines for selecting one from said plurality of memory cells;

a sense amplifier for amplifying a difference between signal levels appearing on said pair of data lines when the stored signal of the memory cell is read out, said sense amplifier comprising first and second circuits;

said first circuit including a pair of cross-coupled N-channel MISFETs coupled to said pair of data lines for bringing about a differential amplification operation, and an N-channel MISFET coupled on the source side of said cross-coupled N-channel MISFETs for controlling the differential amplification operation of said cross-coupled N-channel MISFETs;

said second circuit including a pair of cross-coupled P-channel MISFETs coupled to said pair of data lines for bringing about a differential amplification operation, and a P-channel MISFET coupled on the source side of said cross-coupled P-channel MISFETs for controlling the differential amplification operation of said cross-coupled P-channel MISFETs;

means for supplying first and second timing signals to the gates of said controlling N-channel and P-channel MISFETs, respectively so that the differential amplification operation of said cross-coupled N-channel MISFETs is started at a time different from the time when the differential amplification operation of said cross-coupled P-channel MISFETs is started; and

precharging means for setting said data lines at a potential intermediate between potentials on said data lines to be obtained by operating said amplifier means, after said selecting means operates to place said plurality of memory cells into a non-selected state.

11. A semiconductor memory according to claim 10, wherein said precharging means includes a potential terminal for receiving a potential corresponding to said intermediate potential, a first MISFET having a gate electrode for receiving said control signal, a first electrode coupled to one of said pair of data lines and a second electrode coupled to said potential terminal, and a second MISFET having a gate electrode for receiving said control signal, a first electrode coupled to the other of said pair of data lines and a second electrode coupled to said potential terminal, said first and second MISFETs controlled by said control signal so that said intermediate potential is provided to said data lines via said first and second MISFETs, respectively, after said selecting means operates to place said memory cells into a non-selected state.

12. A semiconductor memory according to claim 11, wherein said intermediate potential corresponds to a potential intermediate between binary signal levels to be stored in the memory cell.

13. A semiconductor memory according to claim 12, wherein said first timing signal occurs prior to the occurrence of said second timing signal so that a pair of said cross-coupled N-channel MISFETs begins its differential amplification operation prior to a pair of said cross-coupled P-channel MISFETs.

14. A semiconductor memory according to claim 12, wherein said second timing signal occurs prior to the occurrence of said first timing signal so that a pair of said cross-coupled P-channel MISFETs begins its differential amplification operation prior to a pair of said cross-coupled N-channel MISFETs.

15. A semiconductor memory according to claim 12, wherein said first circuit further includes another N-channel MISFET connected in parallel with said controlling N-channel MISFET.

16. A semiconductor memory according to claim 15, wherein said another N-channel MISFET has a conductance different from that of said controlling N-channel MISFET, wherein the gate of said another N-channel MISFET is supplied with a third timing signal.

17. A semiconductor memory according to claim 16, wherein said precharging means includes a third MISFET having a gate electrode for receiving said control signal, a first electrode coupled to one of said pair of data lines and a second electrode coupled to the other of said pair of data lines, said third MISFET being controlled by said control signal so that said pair of data lines are electrically coupled to each other after said selecting means operates to place said memory cells into a non-selected state.

18. A semiconductor memory according to claim 10, wherein said intermediate potential corresponds to a potential intermediate between binary signal levels to be stored in the memory cell.

19. A semiconductor memory according to claim 18, wherein said first timing signal occurs prior to the occurrence of said second timing signal so that a pair of said cross-coupled N-channel MISFETs begins its differential amplification operation prior to a pair of said cross-coupled P-channel MISFETs.

20. A semiconductor memory according to claim 18, wherein said second timing signal occurs prior to the occurrence of said first timing signal so that a pair of said cross-coupled P-channel MISFETs begins its differential amplification operation prior to a pair of said cross-coupled N-channel MISFETs.

21. A semiconductor memory according to claim 18, wherein said first circuit further includes another N-channel MISFET connected in parallel with said controlling N-channel MISFET.

22. A semiconductor memory according to claim 21, wherein said another N-channel MISFET has a conductance different from that of said controlling N-channel MISFET, wherein the gate of said another N-channel MISFET is supplied with a third timing signal.

23. A semiconductor memory according to claim 22, wherein said precharging means includes a first MISFET having a gate electrode for receiving a control signal, a first electrode coupled to one of said pair of data lines and a second electrode coupled to the other of said pair of data lines, and first MISFET controlled by said control signal so that said pair of data lines are electrically coupled to each other after said selecting means operates to place said memory cells into a non-selected state.

24. A semiconductor memory according to claim 10, wherein said first timing signal occurs prior to the occurrence of said second timing signal so that a pair of said cross-coupled N-channel MISFETs begins its differential amplification prior to a pair of said cross-coupled P-channel MISFETs.

25. A semiconductor memory according to claim 10, wherein said second timing signal occurs prior to the occurrence of said first timing signal so that a pair of said cross-coupled P-channel MISFETs begins its differential amplification prior to a pair of said cross-coupled N-channel MISFETs.

26. A semiconductor memory according to claim 10, wherein said first circuit further includes another N-channel MISFET connected in parallel with said controlling N-channel MISFET.

27. A semiconductor memory according to claim 26, wherein said another N-channel MISFET has a conductance different from that of said controlling N-channel MISFET, wherein the gate of said another N-channel MISFET is supplied with a third timing signal.

28. A semiconductor memory according to claim 10, wherein said first circuit is coupled on one end side of said pair of data lines while said second circuit is coupled on the other end side of said pair of data lines.

29. A semiconductor memory according to claim 27, wherein said precharging means includes a first MISFET having a gate electrode for receiving a control signal, a first electrode coupled to one of said pair of data lines and a second electrode coupled to the other of said pair of data lines, said first MISFET controlled by said control signal so that said pair of data lines are electrically coupled to each other after said selecting means operates to place said memory cells into a non-selected state.

30. A semiconductor memory formed in a semiconductor integrated circuit comprising:

a pair of data lines disposed substantially parallel and adjacent to each other;

a plurality of word lines, each of which is arranged so as to intersect with both of said pair of data lines;

a plurality of memory cells, each of which is coupled to one of said word lines and one of pair of said data lines at a cross point thereof, and each of which has an address terminal connected to a corresponding word line and a data terminal connected to a corresponding data line;

said each memory cell including a MISFET having a gate electrode connected to said address terminal, a first electrode connected to said data terminal and a second electrode connected to a capacitor;

selecting means coupled to said plurality of word lines for selecting one from said plurality of memory cells;

amplifier means coupled to said pair of data lines for amplifying a potential difference which appears between said data lines in response to selection of one from said plurality of memory cells by said selecting means, wherein said amplifier means includes a pair of first MISFETs of a first conductivity type and a pair of second MISFETs of a second conductivity type, wherein each MISFET of said pair of first MISFETs has its gate cross-coupled to the drain of the other MISFET of said pair of first MISFETs, wherein the drain of one of said pair of first MISFETs is coupled to one of said pair of data lines and the drain of the other of said pair of first MISFETs is coupled to the other of said pair of data lines, wherein each MISFET of said pair of second MISFETs has its gate cross-coupled to the drain of the other MISFET of said pair of second MISFETs, wherein the drain of one of said pair of second MISFETs is coupled to one of said pair of data lines and the drain of the other of said pair of second MISFETs is coupled to the other of said pair of data lines; and

precharging means for setting said data lines at a potential intermediate between potentials on said data lines to be obtained by operating said amplifier means after said selecting means operates to place said plurality of memory cells in a non-selected state.

31. A semiconductor memory according to claim 30, wherein said precharging means includes a potential terminal for receiving a potential corresponding to said intermediate potential, a third MISFET having a gate electrode for receiving a control signal, a first electrode coupled to one of said pair of data lines and a second electrode coupled to said potential terminal, and a fourth MISFET having a gate electrode for receiving said control signal, a first electrode coupled to the other of said pair of data lines and a second electrode coupled to said potential terminal, said third and fourth MISFETs controlled by said control signal so that said potential is provided to said data lines via said third and fourth MISFETs, respectively, after said selecting means operates to place said memory cells into a non-selected state.

32. A semiconductor memory according to claim 31, further comprising control means for controlling the operation of said amplifier means, said control means including first switching means coupled between the source of each of said first MISFETs and a first potential terminal and second switching means coupled between the source of each of said second MISFETs and a second potential terminal.

33. A semiconductor memory according to claim 32, wherein said intermediate potential corresponds to a potential intermediate between binary signal levels to be stored in the memory cell.

34. A semiconductor memory according to claim 33, wherein said precharging means includes a fifth MISFET having a gate electrode for receiving said control signal, a first electrode coupled to one of said pair of data lines and a second electrode coupled to the other of said pair of data lines, said fifth MISFET controlled by said control signal so that said pair of data lines are electrically coupled to each other after said selecting means operates to place said memory cells into a non-selected state.