Semiconductor memory
First Claim
1. A semiconductor memory formed in a semiconductor integrated circuit comprising:
- a pair of data lines which are formed substantially in parallel to each other;
a plurality of word lines, each of which is arranged so as to intersect with both of said pair of data lines;
a plurality of memory cells, each of which is coupled to one of said word lines and to one of said data lines, and each of which includes a MOS transistor of a first conductivity type and a capacitor;
selecting means coupled to said plurality of word lines for selecting one from said plurality of memory cells;
amplifier means coupled to said pair of data lines for amplifying a difference which appears between said data lines in response to selection of one from said memory cells by said selecting means, wherein said amplifier means includes a pair of first MOS transistors of the first conductivity type and a pair of second MOS transistors of a second conductivity type, wherein each transistor of said pair of first MOS transistors has its gate cross-coupled to the drain of the other transistor of said pair of first MOS transistors, wherein the drain of one of said pair of first MOS transistors is coupled to one of said pair of data lines and the drain of the other of said pair of first MOS transistors is coupled to the other of said pair of data lines, wherein each transistor of said pair of second MOS transistors has its gate cross-coupled to the drain of the other transistor of said pair of second MOS transistors, wherein the drain of one of said pair of second MOS transistors is coupled to one of said pair of data lines and the drain of the other of said pair of second MOS transistors is coupled to the other of said pair of data lines; and
precharging means for setting said data lines at a predetermined level between levels on said data lines obtained by operating of said amplifier means after said selecting means makes said memory cells non-selecting state.
1 Assignment
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Accused Products
Abstract
A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the data lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.
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Citations
35 Claims
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1. A semiconductor memory formed in a semiconductor integrated circuit comprising:
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a pair of data lines which are formed substantially in parallel to each other; a plurality of word lines, each of which is arranged so as to intersect with both of said pair of data lines; a plurality of memory cells, each of which is coupled to one of said word lines and to one of said data lines, and each of which includes a MOS transistor of a first conductivity type and a capacitor; selecting means coupled to said plurality of word lines for selecting one from said plurality of memory cells; amplifier means coupled to said pair of data lines for amplifying a difference which appears between said data lines in response to selection of one from said memory cells by said selecting means, wherein said amplifier means includes a pair of first MOS transistors of the first conductivity type and a pair of second MOS transistors of a second conductivity type, wherein each transistor of said pair of first MOS transistors has its gate cross-coupled to the drain of the other transistor of said pair of first MOS transistors, wherein the drain of one of said pair of first MOS transistors is coupled to one of said pair of data lines and the drain of the other of said pair of first MOS transistors is coupled to the other of said pair of data lines, wherein each transistor of said pair of second MOS transistors has its gate cross-coupled to the drain of the other transistor of said pair of second MOS transistors, wherein the drain of one of said pair of second MOS transistors is coupled to one of said pair of data lines and the drain of the other of said pair of second MOS transistors is coupled to the other of said pair of data lines; and precharging means for setting said data lines at a predetermined level between levels on said data lines obtained by operating of said amplifier means after said selecting means makes said memory cells non-selecting state.
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2. A semiconductor memory formed in a semiconductor integrated circuit comprising:
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a pair of data lines disposed substantially parallel and adjacent to each other; a plurality of word lines, each of which is arranged so as to intersect with both of said pair of data lines; a plurality of memory cells, each of which is coupled to one of said word lines and one of said pair of data lines at a cross point thereof, each memory cell having an address terminal connected to a corresponding word line so that each word line is connected to the address terminal of only one memory cell, and having a data terminal connected to a corresponding data line; said each memory cell including a MISFET having a gate electrode connected to said address terminal, a first electrode connected to said data terminal and a second electrode connected to a capacitor; selecting means coupled to said plurality of word lines for selecting one from said plurality of memory cells; amplifier means coupled to said pair of data lines for amplifying a potential difference which appears between said data lines in response to selection of one from said plurality of memory cells by said selecting means, wherein said amplifier means includes a pair of first MISFETs of a first conductivity type and a pair of second MISFETs of a second conductivity type, wherein each MISFET of said pair of first MISFETs has its gate cross-coupled to the drain of the other MISFET of said pair of first MISFETs, wherein the drain of one of said pair of first MISFETs is coupled to one of said pair of data lines and the drain of the other of said pair of first MISFETs is coupled to the other of said pair of data lines, wherein each MISFET of said pair of second MISFETs has its gate cross-coupled to the drain of the other MISFET of said pair of second MISFETs, wherein the drain of one of said pair of second MISFETs is coupled to one of said pair of data lines and the drain of the other of said pair of second MISFETs is coupled to the other of said pair of data lines; and precharging means for setting said data lines at a potential intermediate between potantials on said data lines to be obtained by operating said amplifier means after said selecting means operates to place said plurality of memory cells in a non-selected state. - View Dependent Claims (3, 4, 5, 35)
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6. A semiconductor memory formed in a semiconductor integrated circuit comprising:
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a pair of data lines disposed substantially parallel and adjacent to each other; a plurality of word lines, each of which is arranged so as to intersect with both of said pair of data lines; a plurality of memory cells, each of which is coupled to one of said word lines and one of said pair of data lines at a cross point thereof, each memory cell having an address terminal connected to a corresponding word line so that each word line is connected to the address terminal of only one memory cell, and having a data terminal connected to a corresponding data line; said each memory cell including a MISFET having a gate electrode connected to said address terminal, a first electrode connected to said data terminal and a second electrode connected to a capacitor; selecting means coupled to said plurality of word lines for selecting one from said plurality of memory cells; amplifier means coupled to said pair of data lines for amplifying a potential difference which appears between said data lines in response to selection of one from said plurality of memory cells by said selecting means, wherein said amplifier means includes a pair of first MISFETs of a first conductivity type and a pair of second MISFETs of a second conductivity type, wherein each MISFET of said pair of first MISFETs has its gate cross-coupled to the drain of the other MISFET of said pair of said MISFETs, wherein the drain of one of said pair of first MISFETs is coupled to one of said pair of data lines and the drain of the other of said pair of first MISFETs is coupled to the other of said pair of data lines, wherein each MISFET of said pair of second MISFETs has its gate cross-coupled to the drain of the other MISFET of said pair of second MISFETs, wherein the drain of one of said pair of second MISFETs is coupled to one of said pair of data lines and the drain of the other of said pair of second MISFETs is coupled to the other of said pair of data lines; and precharging means responsive to a control signal for setting said data lines at a potential intermediate between potentials on said data lines to be obtained by operating said amplifier means, after said selecting means operates to place said plurality of memory cells into a non-selected state, wherein said precharging means includes a potential terminal for receiving a potential corresponding to said intermediate potential, a third MISFET having a gate electrode for receiving said control signal, a first electrode coupled to one of said pair of data lines and a second electrode coupled to said potential terminal, and a fourth MISFET having a gate electrode for receiving said control signal, a first electrode coupled to the other of said pair of data lines and a second electrode coupled to said potential terminal, said third and fourth MISFETs being controlled by said control signal so that said potential is provided to said data lines via said third and fourth MISFETs, respectively, after said selecting means operates to place said memory cells in a non-selected state. - View Dependent Claims (7, 8, 9)
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10. A semiconductor memory formed in a semiconductor integrated circuit comprising:
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a pair of data lines disposed substantially parallel and adjacent to each other; a plurality of word lines, each of which is arranged so as to intersect with both of said pair of data lines; a plurality of memory cells, each of which is coupled to one of said word lines and one of said pair of data lines at a cross point thereof, each memory cell having an address terminal connected to a corresponding word line so that each word line is connected to the address terminal of only one memory cell, and having a data terminal connected to a corresponding data line; said each memory cell including a MISFET having a gate electrode connected to said address terminal, a first electrode connected to said data terminal and a second electrode connected to a capacitor; selecting means coupled to said plurality of word lines for selecting one from said plurality of memory cells; a sense amplifier for amplifying a difference between signal levels appearing on said pair of data lines when the stored signal of the memory cell is read out, said sense amplifier comprising first and second circuits; said first circuit including a pair of cross-coupled N-channel MISFETs coupled to said pair of data lines for bringing about a differential amplification operation, and an N-channel MISFET coupled on the source side of said cross-coupled N-channel MISFETs for controlling the differential amplification operation of said cross-coupled N-channel MISFETs; said second circuit including a pair of cross-coupled P-channel MISFETs coupled to said pair of data lines for bringing about a differential amplification operation, and a P-channel MISFET coupled on the source side of said cross-coupled P-channel MISFETs for controlling the differential amplification operation of said cross-coupled P-channel MISFETs; means for supplying first and second timing signals to the gates of said controlling N-channel and P-channel MISFETs, respectively so that the differential amplification operation of said cross-coupled N-channel MISFETs is started at a time different from the time when the differential amplification operation of said cross-coupled P-channel MISFETs is started; and precharging means for setting said data lines at a potential intermediate between potentials on said data lines to be obtained by operating said amplifier means, after said selecting means operates to place said plurality of memory cells into a non-selected state. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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30. A semiconductor memory formed in a semiconductor integrated circuit comprising:
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a pair of data lines disposed substantially parallel and adjacent to each other; a plurality of word lines, each of which is arranged so as to intersect with both of said pair of data lines; a plurality of memory cells, each of which is coupled to one of said word lines and one of pair of said data lines at a cross point thereof, and each of which has an address terminal connected to a corresponding word line and a data terminal connected to a corresponding data line; said each memory cell including a MISFET having a gate electrode connected to said address terminal, a first electrode connected to said data terminal and a second electrode connected to a capacitor; selecting means coupled to said plurality of word lines for selecting one from said plurality of memory cells; amplifier means coupled to said pair of data lines for amplifying a potential difference which appears between said data lines in response to selection of one from said plurality of memory cells by said selecting means, wherein said amplifier means includes a pair of first MISFETs of a first conductivity type and a pair of second MISFETs of a second conductivity type, wherein each MISFET of said pair of first MISFETs has its gate cross-coupled to the drain of the other MISFET of said pair of first MISFETs, wherein the drain of one of said pair of first MISFETs is coupled to one of said pair of data lines and the drain of the other of said pair of first MISFETs is coupled to the other of said pair of data lines, wherein each MISFET of said pair of second MISFETs has its gate cross-coupled to the drain of the other MISFET of said pair of second MISFETs, wherein the drain of one of said pair of second MISFETs is coupled to one of said pair of data lines and the drain of the other of said pair of second MISFETs is coupled to the other of said pair of data lines; and precharging means for setting said data lines at a potential intermediate between potentials on said data lines to be obtained by operating said amplifier means after said selecting means operates to place said plurality of memory cells in a non-selected state. - View Dependent Claims (31, 32, 33, 34)
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Specification