Method of producing semiconductor integrated circuit having parasitic channel stopper region

• US 4,710,265 A
• Filed: 12/04/1986
• Issued: 12/01/1987
• Est. Priority Date: 11/30/1985
• Status: Expired due to Term

• Current Assignee: Nippon Yusen Kabushiki Kaisha
• Original Assignee: Nippon Yusen Kabushiki Kaisha
• Inventors: Hotta, Tadahiko
• Primary Examiner(s): Powell, William A.
• Application Number:
  US06/938,010
• Time in Patent Office: 362 Days
• Field of Search: 29/571, 29/576 B, 29/576 W, 29/578, 148/1.5, 148/187, 148/188, 148/189, 148/190, 148/33, 148/33.1, 148/33.3, 148/33.6, 427/85, 427/93, 156/648, 156/653, 156/657, 156/659.1, 156/661.1, 156/662, 357/42, 357/44
• US Class Current: 438/443
• CPC Class Codes: H01L 21/76218 introducing both types of electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers, e.g. for isolation of complementary doped regions
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: Y10S 438/975 Substrate or mask aligning feature

Abstract

A complementary MOS type integrated circuit is produced by a method which comprises the steps of: disposing a first mask material layer on the surface of a semiconductor substrate, the first mask material layer having a first impurity introducing region corresponding to a desired well forming pattern; forming a well region by selectively doping an impurity into the surface of the substrate through the first impurity introducing region; forming a second mask material layer in such a manner as to cover both the first impurity introducing region and the first mask material layer; disposing first and second mask layers on the second mask material layer, the first and second mask layers respectively corresponding to a first active region pattern within the well region and a second active region pattern outside the well region, thereby defining a second impurity introducing region corresponding to a desired parasitic channel stopper pattern between the stack portion of the first and second mask material layers and the first mask layer; selectively ion-implanting an impurity into the surface of the well region through the second impurity introducing region; selectively removing the first and second mask material layers by selective etching using the first and second mask layers; and selectively thermally oxidizing the surface of the substrate using the remaining portions of the first and second mask material layers as a mask, thereby simultaneously forming a field oxide film and a parasitic channel stopper region containing the implanted impurity. According to this method, the parasitic channel stopper region is self-aligned with both the well region and the field oxide film.

Claims

1. A method of producing a semiconductor integrated circuit, comprising the steps of:

preparing a semiconductor substrate of a first conductivity type and having a principal surface;

disposing a first mask material layer on said principal surface, said first mask material layer having a first impurity introducing region corresponding to a predetermined well forming pattern;

selectively doping a first impurity which determines a second conductivity type, opposite to said first conductivity type, into said principal surface through said first impurity introducing region, thereby forming a well region in said principal surface, said well region having said second conductivity type which is determined by said first impurity;

forming a second mask material layer in such a manner as to cover both said first impurity introducing region and said first mask material layer;

disposing first and second mask layers on said second mask material layer, said first and second mask layers respectively corresponding to a first active region pattern inside said well region and a second active region pattern outside said well region, thereby defining a second impurity introducing region corresponding to a predetermined parasitic channel stopper pattern between the stack portion of said first and second mask material layers and said first mask layer;

selectively ion-implanting a second impurity which determines said second conductivity type into the surface of said well region through said second impurity introducing region;

selectively removing said first and second mask material layers by selective etching using said first and second mask layers; and

carrying out selective thermal oxidation using the remaining portions of said first and second mask material layers as a mask, whereby a field oxide film is formed on said principal surface, and a parasitic channel stopper region is formed within said well region and directly below said field oxide film, said parasitic channel stopper region having said second conductivity type which is determined by said second impurity.

2. A method according to claim 1, wherein said semiconductor substrate is made of silicon, said first and second mask material layers being made of silicon nitride, said method further comprising the step of forming an oxide film which is thinner than said field oxide film on said principal surface prior to the disposition of said first mask material layer on said principal surface.

3. A method of producing a semiconductor integrated circuit, comprising the steps of:

preparing a semiconductor substrate of a first conductivity type and having a principal surface;

disposing a first mask material layer on said principal surface, said first mask material layer having a first impurity introducing region corresponding to a predetermined well forming pattern;

selectively doping a first impurity which determines a second conductivity type, opposite to said first conductivity type, into said principal surface through said first impurity introducing region, thereby forming a first well region in said principal surface, said first well region having said second conductivity type which is determined by said first impurity;

forming an oxide layer corresponding to said first impurity introducing region on said principal surface by selectively oxidizing said principal surface using said first mask material layer as a mask;

selectively doping a second impurity which determines said first conductivity type into said principal surface using said oxide layer as a mask and through said first mask material layer, thereby forming a second well region in said principal surface, said second well region having said first conductivity type which is determined by said second impurity;

etching said oxide layer using said first mask material layer as a mask after said second impurity has been doped;

forming a second mask material layer in such a manner as to cover both said first impurity introducing region and said first mask material layer;

disposing first and second mask layers on said second mask material layer, said first and second mask layers respectively corresponding to a first active region pattern within said first well region and a second active region pattern within said second well region, thereby defining a second impurity introducing region corresponding to a predetermined parasitic channel stopper pattern between the stack portion of said first and second mask material layers and said first mask layer;

selectively doping a third impurity which determines said second conductivity type into the surface of said first well region through said second impurity introducing region;

selectively removing said first and second mask material layers by selective etching using both said first and second mask layers; and

carrying out selective thermal oxidation using the remaining portions of said first and second mask material layers as a mask, whereby a field oxide film is formed on said principal surface, and a parasitic channel stopper region is formed within said first well region and directly below said field oxide film, said parasitic channel stopper region having said second conductivity type which is determined by said third impurity.

4. A method according to claim 3, wherein said first well region is formed by selectively ion-implanting said first impurity into said principal surface through said first impurity introducing region, and said second well region is formed by selectively ion-implanting said second impurity into said principal surface using said oxide layer as a mask and through said first mask material layer.

5. A method according to claim 3, wherein said first well region is formed by selectively and relatively shallowly ion-implanting said first impurity into said principal surface through said first impurity introducing region, and diffusing the ion-implanted first impurity into said principal surface relatively deeply by a heat treatment.

6. A method according to claim 5, wherein said heat treatment for forming said first well region is carried out in an oxidizing atmosphere, whereby said first well region and said oxide layer are simultaneously formed.