Method and apparatus for improving the accuracy and resolution of an analog-to-digital converter (ADC)

• US 4,710,747 A
• Filed: 05/07/1985
• Issued: 12/01/1987
• Est. Priority Date: 03/09/1984
• Status: Expired due to Fees

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Holland, Alex
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US06/731,683
• Time in Patent Office: 938 Days
• Field of Search: 318/631, 340/347 CC, 340/347 AD, 375/26
• US Class Current: 341/120
• CPC Class Codes: H03M 1/0629 Anti-aliasing
• CPC Class Codes: H03M 1/0631 Smoothing
• CPC Class Codes: H03M 1/201 by dithering

Abstract

A system for increasing the accuracy and resolution of an ADC comprising a digital filter connected to the output of the ADC, a system clock for providing a digital filter clock signal, a low/pass filter/amplifier for generating a large-scale, rapidly varying dither signal fdrom the digital filter clock signal, and a summing circuit for adding the dither signal to a test signal connected to the input of the ADC.

Claims

1. A system for improving the accuracy of an analog to digital converter (ADC) of the type having a specified input signal dynamic range (V), and an ADC sampling frequency (f_s), for receiving an analog ADC input signal at an ADC input port, for generating an m-bit digital ADC output signal, and for transferring the digital ADC output signal to an ADC output port, said system comprising:

a system clock for generating a first clock signal at a clock frequency, f_c, and for transferring the first clock signal to a first output port and for generating a second clock signal, at clock frequency, f_s, and for transferring the second clock signal to a second output port;

an analog filter/amplifier, having an input port connected to the first output port of said system clock, for filtering said clock signal to generate a dither signal with frequencies harmonically related to the clock frequency, f_c, for amplifying the dither signal to a selected amplitude substantially covering the input signal dynamic range of the ADC, and for transferring said dither signal to an output port;

an analog summing circuit, having a first port for receiving an analog test signal and a second input port connected to the output port of said analog filter/amplifier, for receiving said dither signal, said analog summing circuit for summing said test and dither signals to form an analog ADC input signal and for transferring said analog ADC input signal to the input port of the ADC, where the amplitude of the analog ADC input signal substantially covers the input dynamic range of the ADC, and where the dither signal is rapidly varying compared to the analog test signal; and

a digital filter, having a first input port for receiving the m-bit digital ADC output signal representing said analog ADC input signal and having a second port for receiving said clock signal, with frequencies of said dither signal locked to the zeros of the digital filter to facilitate attenuation of the dither signal, said digital filters for generating an m+(W)Δ

m bit digital filter output signal representing said analog test signal with (W)Δ

m being the increased resolution of the system.

2. The invention of claim 1 wherein f_s is harmonically unrelated to f_c.

3. A method for improving the accuracy of an analog to digital converter (ADC) of the type having a specified input signal dynamic range (V), and an ADC sampling frequency (f_s), for receiving an analog ADC input signal at an ADC input port, for generating an m-bit digital ADC output signal, and for transferring the digital ADC output signal to an ADC output port, said method comprising the steps of:

selecting an analog test signal having a predetermined amplitude range and bandwidth;

providing a clock signal having a frequency higher than any of the frequencies in the bandwidth of said analog test signal;

deriving an analog dither signal from said clock signal where the dither signal is rapidly varying compared to said analog test signal;

adding said analog dither signal to said analog test signal to form an analog ADC input signal;

controlling the amplitude of said analog dither signal so that the amplitude of said analog input ADC test signal substantially covers the input dynamic range of the ADC;

transferring said analog ADC input signal to the input port of said ADC;

digitally filtering said digital ADC output signal to reduce the amplitude of the dither signal and to increase the accuracy of the ADC; and

utilizing said clock signal to clock said digital filter.

4. The invention of claim 3 further comprising the step of:

selecting the frequency of said digital filter clock signal to be harmonically unrelated to the ADC sampling frequency f_s.

5. The invention of claim 4 further comprising the step of:

selecting the amplitude of said dither signal to be less than 1/2 of V.

6. A system for generating a digital representation of an analog test signal, s(t), comprising:

an analog to digital converter (ADC) for generating an analog ADC input signal, y(t), with said ADC characterized by a given input dynamic range;

means for generating a known dither signal, d(t);

where said dither signal is rapidly varying with respect to said test signal and where the amplitude of d(t) substantially covers the given dynamic range of said ADC;

means for adding d(t) to s(t) to form said analog ADC input signal, y(t); and

means for digitally filtering said m-bit digital signal to attenuate said dither signal.

7. The invention of claim 6 wherein said means for digitally filtering is characterized by a bandpass function with zeros at given frequencies.

8. The invention of claim 7 further including:

means for generating a dither signal having frequency components at frequencies locked to the zeros of said digital filtering means.

9. The invention of claim 8 wherein said means for digitally filtering is synchronized by a clock signal and wherein said means for generating a dither signal comprises:

means for filtering said clock signal; and

means for amplifying said clock signal so that y(t) substantially covers the input dynamic range of said ADC.

10. A system for generating a digital representation of an analog test signal comprising:

an analog to digital converter (ADC) having a specified input signal dynamic range (V), and an ADC sampling frequency (f_s), for receiving an analog ADC input signal at an ADC input port, for generating an m-bit digital ADC output signal, and for transferring the digital ADC output signal to an ADC output port;

a system clock for generating a first clock signal at a clock freuency, f_c, and for transferring the first clock signal to a first output port and for generating a second clock signal, at clock frequency, and for transferring the second clock signal to a f_s, second output port;

an analog filter/amplifer, having an input port connected to the first output port of said system clock, for filtering said clock signal to generate a dither signal with frequencies harmonically related to the clock frequency, f_c, for amplifying the dither signal to a specified amplitude substantially covering the input signal dynamic range of said ADC and for transferring said dither signal to an output port;

an analog summing circuit, having a first input port for receiving an analog test signal and a second input port connected to the output port of said analog filter/amplifier, for receiving said dither signals, said analog summing circuit for summing said test and dither signals to form an analog ADC input signal and for transferring said analog ADC input signal to the input port of the ADC, where the amplitude of the analog ADC input signal substantially covers the input dynamic range of the ADC and where the dither signal is rapidly varying compared to the analog test signal; and

a digital filter, having a first input port for receiving the m-bit digital ADC output signal representing said analog ADC input signal and having a second port for receiving said clock signal, with frequencies of said dither signal locked to the zeros of the digital filter to facilitate attenuation of the dither signal, said digital filter for generating an m+(W)Δ

m bit digital filter output signal representing said analog test signal with (W)Δ

m being the increased resolution of the system.

11. The invention of claim 10 wherein f_s is harmonically unrelated to f_c.