Semiconductor memory device

• US 4,710,789 A
• Filed: 12/03/1986
• Issued: 12/01/1987
• Est. Priority Date: 01/30/1986
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Mashiko, Koichiro, Arimoto, Kazutami, Furutani, Kiyohiro
• Primary Examiner(s): Edlow, Martin H.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/937,206
• Time in Patent Office: 363 Days
• Field of Search: 357/23.6, 357/42, 365/190, 365/51
• US Class Current: 365/149
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H10B 12/37 the capacitor being at least partially in a trench in the substrate

Abstract

In a semiconductor memory device, memory cells of a first column each comprising an N-channel FET are connected to a first bit line, and memory cells of a second column each comprising a P-channel FET are connected to a second bit line. The first bit line and the second bit line are connected to complementary terminals of a sense amplifier to form a folded-bit line pair. A work line is connected to the gate of the N-channel FET of one of the memory cells of the first column and to the gate of the P-channel FET of one of the memory cells of the second column. The word line is selectively provided with a first voltage to make conductive the N-channel FET connected thereto and to make nonconductive the P-channel FET connected thereto, or a second voltage to make conductive the P-channel FET connected thereto and to make nonconductive the N-channel FET connected thereto, or a third voltage to make nonconducitve both the N-channel FET and the P-channel FET connected thereto.

Claims

1. A semiconductor memory device comprising

a plurality of memory cells arranged in rows and columns to form a matrix,

a first bit line to which memory cells of a first column are connected, each of the memory cells of the first column comprising an N-channel FET and capacitance means,

a second bit line to which memory cells of a second column are connected, each of the memory cells of the second column comprising a P-channel FET and capacitance means,

the first bit line and the second bit line being connected to complementary terminals of a sense amplifier to form a folded-bit line pair,

a word line connected to the gate of the N-channel FET of one of the memory cells of the first column and to the gate of the P-channel FET of one of the memory cells of the second column, and

means selectively providing the word line with a first voltage to make conductive the N-channel FET connected thereto and to make nonconductive the P-channel FET connected thereto, or a second voltage to make conductive the P-channel FET connected thereto and make nonconductive the N-channel FET connected thereto, or a third voltage to make nonconductive both the N-channel FET and the P-channel FET connected thereto.

2. A device according to claim 1, wherein a certain number of columns of memory cells having N-channel MOSFETs and the same number of columns of memory cells having P-channel MOSFETs are arranged alternately.

3. A device according to claim 2, wherein a P-type semiconductor region is formed to span the said certain number of columns with the memory cells having the N-channel MOSFETs and an N-type semiconductor region is formed to span the said certain number of columns with the memory cells having the P-channel MOSFETs.

4. A device according to claim 1, wherein the memory cells are arranged in lines orthogonal to the columns, the gates of the MOSFETs of the memory cells arranged in one of the lines are all connected to the same word line.

5. A device according to claim 1, wherein an isolation trench is formed to surround each pair of memory cells sharing a contact hole, each memory cell having a storage capacitor formed at least partially of the capacitance on the sidewall of the isolation trench.