MOS transistor

• US 4,710,790 A
• Filed: 07/03/1984
• Issued: 12/01/1987
• Est. Priority Date: 09/26/1983
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Okamoto, Tatsuo, Eguchi, Kouji, Oosaki, Saburou
• Primary Examiner(s): Edlow, Martin H.
• Application Number:
  US06/627,470
• Time in Patent Office: 1,246 Days
• Field of Search: 357/55, 357/23.4, 357/23.6, 357/23.1
• US Class Current: 257/332
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A gate electrode (4'"'"') of a MOS transistor is formed in a depression (16) provided in a substrate (1). Source and drain regions (6 and 7) of the MOS transistor are formed in the substrate (1) to be opposed to each other with the gate electrode (4'"'"') being located therebetween.

Claims

1. A MOS transistor comprising:

a semiconductor substrate having a depression formed on one major surface thereof;

an insulating film formed at least on an inner bottom surface and a side surface of said depression;

a gate electrode formed in said depression coated with said insulating film; and

a source region and a drain region formed in said major surface of said semiconductor substrate so as to be opposed to each other with said depression being located therebetween, wherein substantially the entire upper surface of said gate electrode is generally flat and approximately even with said major surface of said semiconductor substrate and contained substantially entirely within said depression.

2. A MOS transistor in accordance with claim 1, wherein

a portion of said insulating film on the inner side surface of said depression located between said gate electrode and said source region and a portion of said insulating film on the inner side surface of said depression located between said gate electrode and said drain region are relatively thicker than a portion of said insulating film on the bottom surface of said depression.

3. A MOS transistor in accordance with claim 2, wherein

said relatively thick portions of said insulating film are formed by anisotropic etching.

4. A MOS transistor in accordance with claim 1, further comprising an impurity doping layer formed in a portion of said semiconductor substrate located under the bottom surface of said depression.

5. A MOS transistor in accordance with claim 1, further comprising:

an insulation layer formed on said major surface of said semiconductor substrate including the surface of said gate electrode, said insulating layer having a contact hole being provided therein; and

a wiring made in contact with a desired portion of said gate electrode and said source and drains regions through said contact hole.