Protection device in an integrated circuit

• US 4,710,791 A
• Filed: 07/30/1985
• Issued: 12/01/1987
• Est. Priority Date: 08/09/1984
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Shirato, Takehide, Sekine, Shinichi
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Prenty, Mark
• Application Number:
  US06/760,368
• Time in Patent Office: 854 Days
• Field of Search: 357/23.13, 357/59 F, 357/51, 361/56, 361/91
• US Class Current: 257/363
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An I/O protection device which protects the IC from noise especially from static charge break down is disclosed. A resistance body made from polysilicon is provided between the I/O pad and I/O circuit of the IC. The resistance body may be formed over the gate oxide or field oxide layer. Beneath the resistance body is formed a diffusion region having an opposite conductivity type to that of the substrate. The diffusion region is connected electrically in parallel to the resistance body. In some cases, the diffusion region may be connected at only one point.

Claims

1. A protection device formed on a semiconductor substrate of an IC and connected in a circuit in series with at least one of an input to and output from a circuit formed on said IC, said protection device comprising:

a diffusion region formed on said substrate and having a conductivity type opposite to that of the substrate;

an insulating layer covering said diffusion region;

a resistance body composed of polysilicon formed on said insulating layer over said diffusion region so as to be electrically isolated from said substrate by said diffusion region; and

at least one contact region formed entirely within said diffusion region comprising a layer doped at a higher rate with the same conductivity type of impurity as that of the diffusion region, said resistance body and said diffusion region being electrically connected in parallel through said contact region;

said parallel connected resistance body and diffusion region being connected in series between at least one of an input pad and output pad and said at least one of an input to and output from a circuit.

2. A protection device according to claim 1, wherein said resistance body is formed on a first oxide layer which is fabricated in the same process used for fabricating the oxide film covering the channel region underneath the gate of a FET (Field Effect Transistor) of the IC.

3. A protection device according to claim 1, wherein said resistance body is formed on a field oxide layer of the IC.

4. A protection device according to claim 1, 2 or 3 further comprising:

a second oxide layer covering the surface of the resistance body; and

a passivation film coating the entire surface of the device.

5. A protection device according to claim 4, wherein said passivation film comprises a phosphosilicate glass layer.

6. A protection device according to claim 1, 2 or 3 wherein the time constant of the protection device, determined by the resistance of the resistance body, the resistance of the diffusion region and the capacitance of the resistance body to the substrate, is less than 10% of the time constant of the circuit connected to the protection device.

7. A protection device according to claim 1, wherein said diffusion region forms a diode with said substrate, said diode being biased in the reverse direction by a voltage applied to said substrate.