Interconnect scheme for shared memory local networks
First Claim
1. A data processing system of the type including a plurality of intelligent terminals, a shared memory, and interconnect means for providing access to said shared memory by said intelligent terminals, said interconnect means comprising:
- a plurality of first mapping boxes for receiving first addresses from said intelligent terminals, said first addresses including a virtual address and offset, and for converting said virtual addresses to respective terminal switch port designations and logical addresses;
a first switch having a plurality of first switch ports coupled to said first mapping boxes and having a plurality of second switch ports, said first switch for forwarding said logical addresses and offsets as second addresses to respective second switch ports corresponding to said terminal switch port designations;
a plurality of second mapping boxes for receiving said second addresses and converting said second addresses to respective memory switch port designations and physical addresses; and
a second switch having a plurality of first switch ports for receiving said memory switch port designations and physical addresses and having a plurality of second switch ports connected to address inputs of said shared memory, said second switch for forwarding said physical addresses and offsets to respective second ports of said second switch corresponding to said memory switch port designations.
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Accused Products
Abstract
A plurality of intelligent work stations are provided access to a shared memory through a switching hierarchy including a first array of mapping boxes for receiving a first address from an intelligent work station and including a virtual address and offset and for converting the virtual address into a terminal switch port designation and logical address, a first switch for forwarding the logical address and offset to the designated terminal switch port, a second array of mapping boxes for receiving the logical address and offset and for converting the logical address into a memory switch port designation and physical address, and a second switch for forwarding the physical address and offset to the designated memory switch port as an address to the shared memory.
121 Citations
7 Claims
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1. A data processing system of the type including a plurality of intelligent terminals, a shared memory, and interconnect means for providing access to said shared memory by said intelligent terminals, said interconnect means comprising:
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a plurality of first mapping boxes for receiving first addresses from said intelligent terminals, said first addresses including a virtual address and offset, and for converting said virtual addresses to respective terminal switch port designations and logical addresses; a first switch having a plurality of first switch ports coupled to said first mapping boxes and having a plurality of second switch ports, said first switch for forwarding said logical addresses and offsets as second addresses to respective second switch ports corresponding to said terminal switch port designations; a plurality of second mapping boxes for receiving said second addresses and converting said second addresses to respective memory switch port designations and physical addresses; and a second switch having a plurality of first switch ports for receiving said memory switch port designations and physical addresses and having a plurality of second switch ports connected to address inputs of said shared memory, said second switch for forwarding said physical addresses and offsets to respective second ports of said second switch corresponding to said memory switch port designations. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification