Data transmitting and receiving apparatus
First Claim
1. In a data processing system wherein a plurality of processing devices share a common communication channel by way of which transfer of data messages between a sending processing device and a receiving processing device takes place, an integratd circuit chip associated with each processing device for generating a data message comprising the acknowledgement of the receipt and the received condition of a data message transmitted between the sending processing device and the receiving device, said chip comprising:
- means for generating a plurality of first control signals identifying the condition of the data message received from a sending processing device;
first logic circuit means connected to said generating means for outputting a second control signal in response to receiving said first control signals;
a shift register means connected to said generating means and said first logic circuit means for outputting a portion of an acknowledgement message comprising a sequence of two pairs of binary data bits which includes a pair of first binary data bits identifying the condition of the data message receiver from the sensing processing device and a pair of second binary data bits preceding the least significant bit of each of said first binary data bits for use in framing and decoding said first binary data bits in response to receiving said first and second control signals;
transmitting means connected to said communication channel and to said shift register means for repeatedly transmitting said pairs of said first and second binary data bits over said communication channel to the sending processing device a predetermined number of times comprising the acknowledgement message acknowledging the receipt of said data message from the sending device in which each pair of first binary data bits are framed by two pairs of said second binary data bits; and
timing means connected to said transmitting means for disabling said transmitting means after said transmitting means has repeatedly transmitted the sequence of pairs of said first and second binary data bits said predetermined number of times over said communication channel.
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Accused Products
Abstract
A system for controlling the transfer of a data message over a common communication channel between a plurality of processing devices includes a MOS/LSI controller chip associated with each processing unit for constructing a message to be sent to a sending device acknowledging the receipt of the message and the validity of the message. Logic circuits are included which generate a predetermined sequence of two binary bits indicating the receipt of the message and the validity of the receiving message. The binary bits are framed by two other binary bits and the sequence repeated a predetermined number of times to construct an acknowledgment message. The controller chip further includes logic circuits for decoding the acknowledgment message.
121 Citations
8 Claims
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1. In a data processing system wherein a plurality of processing devices share a common communication channel by way of which transfer of data messages between a sending processing device and a receiving processing device takes place, an integratd circuit chip associated with each processing device for generating a data message comprising the acknowledgement of the receipt and the received condition of a data message transmitted between the sending processing device and the receiving device, said chip comprising:
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means for generating a plurality of first control signals identifying the condition of the data message received from a sending processing device; first logic circuit means connected to said generating means for outputting a second control signal in response to receiving said first control signals; a shift register means connected to said generating means and said first logic circuit means for outputting a portion of an acknowledgement message comprising a sequence of two pairs of binary data bits which includes a pair of first binary data bits identifying the condition of the data message receiver from the sensing processing device and a pair of second binary data bits preceding the least significant bit of each of said first binary data bits for use in framing and decoding said first binary data bits in response to receiving said first and second control signals; transmitting means connected to said communication channel and to said shift register means for repeatedly transmitting said pairs of said first and second binary data bits over said communication channel to the sending processing device a predetermined number of times comprising the acknowledgement message acknowledging the receipt of said data message from the sending device in which each pair of first binary data bits are framed by two pairs of said second binary data bits; and timing means connected to said transmitting means for disabling said transmitting means after said transmitting means has repeatedly transmitted the sequence of pairs of said first and second binary data bits said predetermined number of times over said communication channel. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification