Random access memory with error correction capability

• US 4,710,934 A
• Filed: 11/08/1985
• Issued: 12/01/1987
• Est. Priority Date: 11/08/1985
• Status: Expired due to Fees

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Traynor, Kevin
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): Beausoliel, Jr., Robert W.
• Application Number:
  US06/796,367
• Time in Patent Office: 753 Days
• Field of Search: 371/38, 371/51, 371/13, 371/21, 365/200
• US Class Current: 714/765
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems

Abstract

A Random Access Memory with error detection/correction capability includes an information array (10) for storage of a collective data word in a single row thereof and a parity array (12) for storage of corresponding parity information in a single row thereof. A single row of the information array (10) and the parity array (12) are accessed and input to an error correct circuit (54). The collective data and parity information are also input to an error syndrome/parity generator (48), the output of which is input to the error correct circuit (54) to correct bits that are in error. A latch (72) is provided for latching the corrected information therein to allow new data to be written therein. The output of the latch (72) is multiplexed into the error syndrome/parity generator (48) which is configurable as a parity generator to generate new parity information for a write operation. The new collective data and parity information in the write mode are stored in arrays (10) and (12).

Claims

1. A read/write memory, comprising:

a plurality of data memory cells arranged in rows and columns;

a plurality of code memory cells arranged in rows and columns;

each row of said code memory cells for storing an error detection code corresponding to a row of said data memory cells;

row addressing means for selecting a row of said data memory cells and the corresponding row of said code memory cells;

sensing means for sensing the contents of each data memory cell and each said code memory cell in the row selected by said row addressing means and for writing the contents of said data memory cells and said code memory cells in the selected row;

error detection logic, connected to said sensing means, for detecting an error in the sensed contents of said data memory cells and the contents of the associated code memory cells by way of a predetermined code;

error correction logic, connected to said error detection logic and to said sensing means, for modifying the sensed output for a data memory cell corresponding to an error detected by said error detection logic;

column addressing means for selecting a data memory cell to be read or written responsive to a column address signal;

input/output means, connected to said column addressing means, for externally presenting the modified contents of the selected data memory cell in a read cycle, and for receiving data to be written to the selected data memory cell in a write cycle;

read/write logic, for controlling said input/output means to present data responsive to a read signal, and for controlling said input/output means to receive data in a write cycle;

a data latch having a bit position for each data memory cell in a row, connected to the output of said error correction logic, for storing the output of said error correction logic, and connected to said input/output means and said read/write logic so that, in a write cycle, the bit position corresponding to the data memory cell selected by said column addressing means therewithin is rewritten with the data received by said input/output means;

a data rewrite bus, connected to said data latch and to said sensing means, for communicating the contents of said data latch to said sensing means for application to the data memory cells in the selected row; and

code generation means, connected to said data rewrite bus and to said sensing means, for generating the contents of the code memory cells for the selected row, based upon the contents of said data latch, for application to the code memory cells in the selected row.

2. The memory of claim 1, wherein said error detection means comprises:

error syndrome logic, connected to said sensing means, for calculating an error syndrome according to a predetermined code, based upon the sensed contents of the data memory cells and the code memory cells in the selected row; and

an error position decoder, connected to the output of the error syndrome logic, for presenting to said error correction means the location of the data memory cell in error.

3. The memory of claim 1, wherein said error correction logic is also for modifying the sensed contents of said code memory cells in the event of an error therein;

and further comprising;

a code latch, connected to the output of said error correction logic, having a bit position for each code memory cell in said row, for storing the modified contents of the sensed code memory cells in the selected row;

a code rewrite bus, connected to said sensing means and to said code latch, for communicating the contents of said code latch to said sensing means for application to said code memory cells in the selected row.

4. The memory of claim 3, wherein said sensing means is also for applying the contents of said data latch to said data memory cells in the selected row and for applying the contents of said code latch to said code memory cells in the selected row after each read cycle, thereby refreshing said memory cells in the selected row.

5. The memory of claim 4, wherein said sensing means is also for applying the contents of said data latch to said data memory cells in the selected row and for applying the contents of said code latch to said code memory cells in the selected row in a refresh cycle, thereby refreshing said memory cells in the selected row;

and wherein said input/output means and said column addressing means are disabled during said refresh cycle.

6. The memory of claim 1, wherein said column addressing means selects a plurality of said data memory cells.

7. The memory of claim 1, wherein said memory cells are dynamic read/write memory cells.

8. A read/write memory, comprising:

a plurality of data memory cells arranged in rows and columns;

a plurality of code memory cells arranged in rows and columns, each row of said code memory cells for storing an error detection code corresponding to a row of said data memory cells;

row addressing means for selecting a row of said data memory cells and the corresponding row of said code memory cells;

sensing means for sensing the contents of each data memory cell and each said code memory cell in the row selected by said row addressing means and for writing the contents of said data memory cells and said code memory cells in the selected row;

parity/syndrome logic, connected to said sensing means, operative during a first part of the memory cycle to calculate an error syndrome according to a predetermined code based upon the sensed contents of the sensed data memory cells and the code memory cells from the selected row;

an error position decoder, connected to the output of the parity/syndrome logic, for determining the location of the data memory cell in error based upon the error syndrome calculated by said parity/syndrome logic;

error correction logic, connected to said error position decoder and to said sensing means, for modifying the sensed output of a data memory cell corresponding to an error detected by said parity/syndrome logic;

column addressing means for selecting a data memory cell to be read or written responsive to a column address signal;

input/output means, connected to said column addressing means, for externally presenting the modified contents of the selected data memory cell in a read cycle, and for receiving data to be written to the selected data memory cell in a write cycle;

read/write logic, for controlling said input/output means to present data responsive to a read signal, and for controlling said input/output means to receive data in a write cycle;

a data latch having a bit position for each data memory cell in a row, connected to the output of said error correction logic, for storing the output of said error correction logic, and connected to said input/output means and said read/write logic so that, in a write cycle, the bit position corresponding to the data memory cell selected by said column addressing means therewithin is rewritten with the data received by said input/output means; and

a data rewrite bus, connected to said data latch and to said sensing means, for communicating the contents of said data latch to said sensing means for application to the data memory cells in the selected row;

wherein said parity/syndrome logic is connected to said data rewrite bus, and is operative during a second part of the memory cycle for calculating the contents of said code memory cells in the selected row, based upon the contents of said data latch, for application to the code memory cells in the selected row.

9. The memory of claim 8, wherein said column addressing means selects a plurality of said data memory cells.

10. The memory of claim 8, wherein said memory cells are dynamic read/write memory cells.

11. The memory of claim 8, wherein said predetermined code is a Hamming code.

12. The memory of claim 8, further comprising:

a data register having a bit position for each of the data memory cells in the selected row;

transfer means, connected between said output of said error correction logic and said data register, for communicating the output of said error correction logic to said data register responsive to a transfer signal and for isolating said data register from said output of said error correction logic in the absence of said transfer signal; and

a serial output, connected to said data register, for serially presenting the contents of said data register responsive to a series of clock signals.