Pattern recognition apparatus using oscillating memory circuits

• US 4,710,964 A
• Filed: 07/07/1986
• Issued: 12/01/1987
• Est. Priority Date: 07/06/1985
• Status: Expired due to Term

• Current Assignee: Research Development Corporation Of Japan (Japan Science And Technology Agency)
• Original Assignee: Research Development Corporation Of Japan (Japan Science And Technology Agency)
• Inventors: Shimizu, Hiroshi, Tsuda, Ichiro, Yamaguchi, Youko, Yano, Masafumi, Okumura, Tokiko
• Primary Examiner(s): Boudreau, Leo H.
• Assistant Examiner(s): Brim, Steven
• Application Number:
  US06/882,470
• Time in Patent Office: 512 Days
• Field of Search: 382/21, 382/17, 382/29, 382/64
• US Class Current: 382/191
• CPC Class Codes: G06V 10/454 Integrating the filters into a hierarchical structure, e.g. convolutional neural networks [CNN]

Abstract

A pattern recognition apparatus includes a pattern preprocessing part having a plurality of outputs, and a clock oscillator, an information consolidator and a memory having a plurality of nonlinear oscillating circuits, respectively. Each of the oscillating circuits includes a plurality of inputs for controlling the oscillation condition and at least one output. In the information consolidator, the output of each oscillating circuit is interconnected to predetermined inputs of other oscillating circuits in a predetermined relation, and the inputs of the oscillating circuits are coupled to the outputs of the pattern preprocessing part in a predetermined distribution. The clock oscillator receives, as a main exciting signal, the sum of a group of signals obtained by phase-adjusting the output of a substantial part of oscillating circuits contained in the information consolidator. In the memory, the respective oscillating circuits receive as a main exciting signal the output of the clock oscillator, and these oscillating circuits are divided into a predetermined number of groups so that the sum of the outputs of the oscillating circuits in each group gives an elementary signal of a pattern reference memory data. In addition, there is provided a waveform comparator for comparing the elementary signal of the memory data with the direct sum of the outputs of the above mentioned substantial part of oscillating circuits in the information consolidator, so that the result of comparison is applied to inputs of the oscillating circuits of the memory.

Claims

1. A pattern recognition apparatus which includes a pattern preprocessing part having a plurality of outputs, a clock oscillator, and an information consolidator and a memory having a plurality of nonlinear oscillating circuits, respectively, characterized in that

each of the oscillating circuits includes a plurality of inputs for controlling the oscillation condition and at least one output;

the output of each oscillating circuit in the information consolidator being interconnected to predetermined inputs of other oscillating circuits in a predetermined relation, and the inputs of the oscillating circuits being coupled to the outputs of the pattern preprocessing part in a predetermined distribution;

the clock oscillator being connected to receive as a main exciting signal, the sum of a group of signals obtained by phase-adjusting the outputs of a substantial part of oscillating circuits contained in the information consolidator;

the respective oscillating circuits in the memory being connected to receive, as a main exciting signal, the output of the clockoscillator, and said oscillating circuits also being divided into a predetermined number of groups so that the sum of the outputs of the oscillating circuits in each group given an elementary signal of a pattern reference memory data; and

further including waveform comparison means for comparing the elementary signal of the memory data with the direct sum of the outputs of the said substantial part of oscillating circuits in the information consolidator, so that the result of comparison is applied to inputs of the oscillating circuits of the memory.

2. An apparatus as claimed in claim 1 wherein the oscillating circuits in the information consolidator are divided into a plurality of groups, each including a plurality of oscillating circuits, the respective groups of the oscillating circuits being assigned to respective partial planes of a plane capable of representing an output pattern of the preprocessing part, and the oscillating circuits in the information consolidator being connected at their predetermined inputs to the preprocessing part in such a manner that all the oscillating circuits contained in respective oscillating circuit groups corresponding to the partial planes on which respective segments of the output pattern from the preprocessing part are positioned are excited.

3. An apparatus as claimed in claim 2 wherein each group of oscillating circuits includes oscillating circuits respectively corresponding to possible directions of the segments each of which is dissolved from the contour of the given pattern and passes through one partial plane of the above mentioned plane, each said oscillating circuits being connected at its output to adjacent oscillating circuits having the same or opposite directivity to that oscillating circuit so as to strongly excite said adjacent oscillating circuits, each oscillating circuits being connected at its output to adjacent oscillating circuits having the directivity perpendicular to that of the oscillating circuit so as to weaken the oscillation of said adjacent oscillating circuits, and each oscillating circuits being connected to neighbor oscillating circuits in such a manner as to strongly excite the oscillating circuits having directivities diverging from an oscillating circuit adjacent to the above mentioned oscillating circuit in its directivity, but to weaken the oscillation of the oscillating circuits having directivities converging to the above segment oscillating circuit.

4. An apparatus claimed in claim 3 wherein each of the oscillating circuits includes at least one input for magnifying its output and at least one input for weakening its output.

5. An apparatus claimed in claim 4 wherein each nonlinear oscillating circuit is of the van der pole type.