Solid-state cumulative operations measurement system

• US 4,712,195 A
• Filed: 05/09/1986
• Issued: 12/08/1987
• Est. Priority Date: 05/09/1986
• Status: Expired due to Term

• Current Assignee: Curtis Instruments Incorporated
• Original Assignee: Curtis Instruments Incorporated
• Inventors: Finger, Eugene P.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/861,339
• Time in Patent Office: 578 Days
• Field of Search: 365/201, 365/189, 365/230, 365/233, 365/149, 365/228, 365/229, 365/226
• US Class Current: 365/226
• CPC Class Codes: G07C 3/04 using counting means or digital clocks
• CPC Class Codes: H03K 21/403 Arrangements for storing the counting state in case of power supply interruption

Abstract

The system accurately measures a summation of the operations when an operating voltage is present. The system includes a capacitor charged by a supply voltage and a volatile memory register connected to receive the operating voltage signals to be measured and operable to store those signals as a measure of operations. A nonvolatile memory register is provided having stages corresponding to the stages of the volatile memory register. A store sequencing means is connected to be powered by the energy stored in the capacitor when the supply voltage is removed to transfer the count stored in the volatile memory register into the nonvolatile memory register. A means is provided for detecting when the supply voltage is applied, with a recall sequencing means operable in response thereto to transfer the count stored in the nonvolatile memory register into the volatile memory register.

Claims

1. A cumulative operations measurement system for connection to a source of supply voltage and operable in response to an operating voltage for accurately measuring a summation of the operations when that operating voltage is present, said system comprising a capacitor connected to be charged by the supply voltage, a volatile multiple-stage memory register connected to receive the operating voltage signals to be counted at the low order end thereof and operable to store said signals as a measure of total operations, a nonvolatile multiple-stage memory register having stages corresponding to at least some of the stages of said volatile memory register, means for detecting when the supply voltage is removed, a store sequencing means connected to be powered by the energy stored in said capacitor and connected to said last-named means and operable in response thereto to transfer the count stored in said volatile memory register into said nonvolatile memory register for storage therein, means for detecting when the supply voltage is applied. a recall sequencing means connected to said last-named means and operable in response thereto to transfer the count stored in said nonvolatile memory register into said volatile memory register.

2. A cumulative operations measurement system as claimed in claim 1 wherein the operating voltage is the supply voltage and the summation of the operations when the operating voltage is present is taken by measuring the elapsed time during which the operating voltage is present and wherein there is provided an oscillator, and wherein said volatile memory register is connected to receive electrical operations signals in the form of output pulses from said oscillator and wherein the storage of said signals is a measure of total operations time.

3. A system as claimed in claim 2 wherein a frequency divider is connected between said oscillator and said volatile memory register for dividing the frequency of said oscillator down to conventional unit of time.

4. A system as claimed in claim 1 wherein the summation of the operation when the operation voltage is present is taken by measuring the elapsed time during which the operating voltage is present and wherein the summation of operations is also taken by counting and summing the number of times that the operating voltage rises to an operating value, and wherein said volatile memory register and said nonvolatile memory register both include sections for the respective storage of a summation of the elapsed time during which the operating voltage is present and for storing a summation of the count of the number of times that the operating voltge rises to an operating value.

5. A system as claimed in claim 4 which is also operable for storing an identification number and wherein said volatile memory register includes still another section for the storage of the identification number, and wherein said nonvolatile memory also includes the capacity for storage of the identification number.

6. A system as claimed in claim 1 wherein at least one resistor is connected in series in the line from the supply voltage to said capacitor to form a filter element in association with said capacitor.

7. A system as claimed in claim 1 wherein there is provided a maximum voltage limiter device arranged for connection in shunt with said capacitor for limiting the maximum voltage applied across said capacitor and to the system beyond said capacitor.

8. A system as claimed in claim 1 wherein there is included a maximum impedance limit circuit connected in shunt with said capacitor to determine the maximum discharge impedance for said capacitor.

9. A system as claimed in claim 1 wherein said store sequencing means is operable to accomplish said transfer by comparing the binary value stored in each stage of said nonvolatile memory with the binary value stored in each corresponding stage of said volatile memory register and by initiating a write operation to change the state of only those stages in the nonvolatile memory which must be changed to coincide with the state of the corresponding stages in said volatile memory register.

10. A system as claimed in claim 1 which includes at least two voltage threshold circuits which are operable for receiving and comparing a voltage representative of the operating voltage with a different fixed threshold voltage value for each threshold circuit, one of said voltage threshold circuits having a higher fixed threshold voltage value than the other, and wherein aid means for detecting when the operating voltage is applied comprises a first voltage sequence detection circuit connected to said voltage threshold circuits and operable to detect the sequence wherein the lower voltage threshold is passed and then the upper voltage threshold is passed by the operating voltage, and wherein said means for detecting when the operating voltage is removed comprises a second voltage sequence detection circuit connected to said threshold voltage circuits and operable to detect when the operating voltage is removed by detecting a sequence in which the higher voltage threshold is passed and then the lower voltage threshold is passed by the operating voltage.

11. A system as claimed in claim 10 wherein separate lower threshold voltage circuits are provided respectively for said first voltage sequence detection circuit and said second voltage sequence detection circuit, the lower voltage threshold for said second voltage sequence detector for detecting when the operating voltage is removed being higher than the lower voltage threshold for said first voltage sequence detector for detecting when the operating voltage is applied.

12. A system as claimed in claim 11 wherein a circuit means is provided which is connected between the output of one of said lower threshold voltage circuits and an input of said store sequencing means to disable said store sequencing means at all voltage levels below the threshold of said last-named lower threshold circuit.

13. A system as claimed in claim 10 wherein a circuit means is connected between an output of said first voltage sequence detector and the upper threshold voltage level input of said second voltage sequence detector for signifying to said second voltage sequence detector that the operating voltage has achieved a level above said upper threshold voltage level, said circuit means being operable to provide a signal to said second voltage sequence detector for the upper threshold voltage only after there is an output from said first voltage sequence detector recognizing that the operating voltage has been applied so that said second voltage sequence detector is operable to detect the declining sequence of voltages to actuate said store sequencing means only after said first voltage sequence detector has been operable to actuate said recall sequencing means.

14. A system as claimed in claim 13 wherein said circuit means connected between the output of said first voltage sequence detector and the upper threshold voltage input of said second voltage sequence detector comprises a rearm timer which is operable to delay the delivery of a signal from the output of said first voltage sequence detector so that said second voltage sequence detector is only operable to detect a decreasing voltage sequence after the time delay provided by said rearm timer, said first voltage sequence detector being operable to detect a declining voltage sequence and to withdraw the output signal to said rearm timer in response to the declining voltage sequence, said rearm timer being automatically resettable upon withdrawal of the output signal from said first voltage sequence detector before the rearm timer has timed out.

15. A system as claimed in claim 14 wherein said rearm timer includes means for selectively changing the time delay interval.

16. A system as claimed in claim 14 wherein a circuit means is connected between the output of said upper threshold voltage circuit and an enabling input to said volatile memory register, said circuit means being operable for enabling said volatile memory register to receive and count operations signals only while the operating voltage is above the threshold voltage of said upper threshold voltage circuit.

17. A system as claimed in claim 16 wherein said last-named circuit means is operable for enabling said volatile memory register to receive and count operations signals only after a time delay interval which assures that the recall sequencing means has completed the recall sequence of recalling the data stored in said nonvolatile memory into said volatile memory register.

18. A system as claimed in claim 17 wherein said last-named circuit means includes a time delay means and an AND gate, said AND gate being operable only in response to a coincidence of a signal indicating that the operating voltage is above the threshold level and a time delayed signal available after a time delay interval after the operating voltage is above the threshold voltage of said upper threshold voltage circuit.

19. A system as claimed in claim 18 wherein said time delay means comprises a connection from said recall sequencing means for sending a signal to said AND gate indicating that the recall sequence has been completed, said AND gate being operable only after the completion of a recall sequence and the coincidence of an output from said upper threshold voltage circuit to enable said volatile memory register to receive and count operations signals.

20. A system as claimed in claim 1 wherein there is provided a diode connected in series in the connections to the source of operating voltage to accommodate the system to alternating operating voltage, and to isolate the system from the impedance of the source of operating voltage.

21. A system as claimed in claim 1 including a serial encoder connected to receive parallel readout data from said volatile memory register and operable to provide a chain of binary bits corresponding to the contents of said volatile memory register in serial form, an output buffer memory connected to receive the serial chain of binary bits from said serial encoder, and an output connection from said output buffer for sending the serial output signals to a reader device.

22. A system as claimed in claim 21 including a separable reader device operable for receiving and interpreting the chain of binary signals from said output buffer, said serial encoder and said output buffer being operable for generating marker signals to indicate the beginning of a chain of data signals, and said reader device including means for recognizing said marker signals and for interpreting the chain of digital signals based upon timing established by said marker signals.

23. A system as claimed in claim 1 wherein the summation of the operations when the operating voltage is present is taken by counting and summing the number of times that the operating voltage rises to an operating value and wherein each of said electrical operations signals actuates said volatile memory register for incrementation by a single count.

24. A system as claimed in claim 23 wherein the operating voltage for which operations are to be measured is the supply voltage.

25. A system as claimed in claim 23 wherein a signal channel is provided for the operating voltage which includes a digital low-pass filter.

26. A system as claimed in claim 1 which includes an oscillator, and which also includes a conversion circuit selectively operable in response to conversion control signals to optionally select a first mode of operation for the system wherein the measurement of the summation of the operations when the operation voltage is present is obtained by measuring the total elapsed time during which said operating voltage is present and summing those elapsed times, and to optionally select a select mode of operation for the system wherein the measurement of the summation of the operations when the operating voltage is present is obtained by measuring each occurrence of the presence of the operating voltage and counting and summing the counts of those occurrences of the operating voltage.