Cache memory consistency control with explicit software instructions

• US 4,713,755 A
• Filed: 06/28/1985
• Issued: 12/15/1987
• Est. Priority Date: 06/28/1985
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Company (HP Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Baum, Allen, Worley, William S. Jr., Bryg, William R.
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US06/750,381
• Time in Patent Office: 900 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/123
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0837 with software control, e.g. non-cacheable data
• CPC Class Codes: G06F 9/3812 with instruction modification, e.g. store into instruction stream
• CPC Class Codes: Y10S 707/99934 Query formulation, input preparation, or translation

Abstract

Memory integrity is maintained in a system with a hierarchical memory using a set of explicit cache control instructions. The caches in the system have two status flags, a valid bit and a dirty bit, with each block of information stored. The operating system executes selected cache control instructions to ensure memory integrity whenever there is a possibility that integrity could be compromised.

Claims

1. A computer system having a multi-level memory hierarchy and means for maintaining the integrity of blocks of information stored at different levels in the hierarchy, comprising:

a processor for executing instructions and processing data, said processor executing a set of instructions for providing explicit control of the transfer of blocks of data between levels of the memory hierarchy;

memory for storing instructions and data;

an I/O channel connected to the memory for transferring data and instructions into and out of the memory;

a cache connected between the processor and the memory for storing selected blocks of information from the memory for use by the processor, and having associated with each stored block a valid status flag and a dirty status flag; and

an operating system resident in memory and accessible by the processor, containing the instructions in the instruction set, for causing the execution of certain of the instructions from the instruction set to ensure the consistency of the information stored in the cache with the information transferred into and out of memory.

2. The computer system of claim 1 wherein,

the instruction set comprises Flush Data Cache, Purge Data Cache, Flush Instruction Cache, Flush Data Cache Entry, Flush Instruction Cache Entry and Synchronize Caches instructions;

and

prior to transfer of data or instructions into or out of memory via the I/O channel, the operating system broadcasts the Flush Data Cache and Flush Instruction Cache instructions to the cache over the range of addresses into which or out of which data is transferred.

3. The computer system of claim 2 wherein the multi-level memory hierarchy is implemented as a virtual memory system including main memory and peripheral memory and, when a page or a segment is removed from main memory to a peripheral memory, the operating system broadcasts the Flush Data Cache and Flush Instruction Cache instructions to the cache over the range of addresses in the page or segment;

when a page or segment is destroyed, the operating system broadcasts the Purge Data Cache and Flush Instruction Cache instructions to the cache over the range of addresses in the page or segment.

4. The computer system of claim 2 wherein,

the cache is divided into two segments, a data cache for storing data and an instruction cache for storing instructions;

instructions can be modified when stored as part of a block of data in the data cache; and

after modification of an instruction, the operating system issues the Flush Data Cache instruction to the data cache for the address of the block including the modified instruction, issues the Flush Instruction Cache instruction to the instruction cache for the address of the modified instruction and then executes the Synchronize Caches instruction.

5. The computer system of claim 2 wherein, in the event of a processor failure, the operating system executes a routine including the Flush Data Cache Entry and Flush Instruction Cache Entry instructions over the index range for the data cache and for the instruction cache.