Programmable macrocell using eprom or eeprom transistors for architecture control in programmable logic circuits

• US 4,713,792 A
• Filed: 06/06/1985
• Issued: 12/15/1987
• Est. Priority Date: 06/06/1985
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Chan, Yiu-Fai, Wong, Sau-Ching, Hartmann, Robert F., Ou, Jung-Hsing, Frankovich, Robert J., So, Hock C.
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US06/742,089
• Time in Patent Office: 922 Days
• Field of Search: 364/900 MS File
• US Class Current: 711/103
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 19/1736 in which the wiring can be modified
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence

Abstract

A programmable macrocell 28 for use in an integrated circuit device including an electronic circuit 32 responsive to control signals and operative to perform particular operations selected by the control signals on input data signals and to develop commensurate output signals, and one or more architecture control circuits 30 each including a programmable EPROM device 34 which when programmed generates a logic signal of a first state and when unprogrammed generates a logic signal of a second state, a read and write control circuit 36 responsive to input program data signals and a corresponding address signal and operative to program the EPROM device 34 by applying a programming potential thereto, and a sensing circuit 38 for sensing the programmed or unprogrammed status of the EPROM device 34 and for developing a commensurate control signal for input to the electronic circuit 32.

Claims

1. A programmable macrocell in an integrated circuit device comprising:

electronic circuit means responsive to a program control signal and operative to perform a particular operation selected by said control signal on an input data signal and to develop a commensurate output data signal, said electronic circuit means including an inversion control circuit having exclusive NOR gate means with one input thereof receiving said control signal and another input thereof receiving said input data signal; and

architecture control means including one or more architecture control circuits each having

a programmable EPROM device having gate, drain and source electrodes and which when programmed generates a logic signal of a first state and when unprogrammed generates a logic signal of a second state,

read and write control means connected to said EPROM device and responsive to an input program data signal and a corresponding address signal and operative to program said EPROM device by applying a programming potential thereto, and

sense means connected to said EPROM device for sensing the programmed or unprogrammed state of said EPROM device and for developing a commensurate control signal for input to said inversion control circuit,

whereby in response to said control signal said inversion control circuit causes an input data signal to be inverted when an associated EPROM device is in said first state and to be not inverted when said EPROM device is in said second state.

2. A programmable macrocell as recited in claim 1 wherein said read/write control means includes a programming circuit responsive to said program data signals and operative to apply said programming potential to the drain electrode of said EPROM device, a NOR gate responsive to said address signal and operative to develop a logic output, and switching means responsive to said logic output of said NOR gate and operative to couple said programming potential to the gate electrode of said EPROM device to effect programming thereof.

3. A programmable macrocell as recited in claim 2 wherein said architecture control circuits are implemented using EEPROM devices rather than EPROM devices.

4. A programmable macrocell as recited in claim 2 wherein said programming circuit includes a first transistor switching element for coupling said programming potential to the drain electrode of said EPROM device and an inverting circuit coupled to the gate electrode thereof for inverting said program data signal.

5. A programmable macrocell as recited in claim 4 wherein said architecture control circuits are implemented using EEPROM devices rather than EPROM devices.

6. A programmable macrocell as recited in claim 4 wherein said sense means includes a Schmidt trigger circuit coupled to the drain electrode of said EPROM device and operative to develop a control signal corresponding to the state of the logic signal generated by said EPROM device.

7. A programmable macrocell as recited in claim 6 wherein said architecture control circuits are implemented using EEPROM devices rather than EPROM devices.

8. A programmable macrocell as recited in claim 1 wherein said architecture control circuits are implemented using EEPROM devices rather than EPROM devices.

9. A programmable macrocell in an integrated circuit device comprising:

architecture control means including a plurality of architecture control circuits each having

a programmable EPROM device including gate, drain and source electrodes which when programmed generates a logic signal of a first state and when unprogrammed generates a logic signal of a second state,

read and write control means connected to said EPROM device and responsive to an input program data signal and a corresponding address signal and operative to program said EPROM device by applying a programming potential thereto, and

sense means connected to said EPROM device for sensing the programmed or unprogrammed state of said EPROM device and for developing a commensurate control signal; and

electronic circuit means responsive to said control signals and operative to perform particular operations selected by said control signals on input data signals and to develop commensurate output data signals, said electronic circuit means including a digital multiplexer means having a plurality of AND gates each of which receives at least one input data signal and a control signal developed by said architecture control means, the outputs of said AND gates being ORed together in an output OR gate which in turn develops an output signal corresponding to one of said input data signals as selected by a particular one of said control signals.

10. A programmable macrocell as recited in claim 9 wherein said read and write control means includes a programming circuit responsive to said program data signal and operative to apply said programming potential to the drain electrode of said EPROM device, a NOR gate responsive to said address signal and operative to develop a logic output, and switching means responsive to said logic output of said NOR gate and operative to couple said programming potential to the gate electrode of said EPROM device to effect programming thereof.

11. A programmable macrocell as recited in claim 10 wherein said programming circuit includes a first transistor switching element for coupling said programming potential to the drain of said EPROM device and an inverting circuit coupled to the gate electrode thereof for inverting said program data signal.

12. A programmable macrocell as recited in claim 11 wherein said sense means includes a Schmidt trigger circuit coupled to the drain electrode of said EPROM device and operative to develop a control signal corresponding to the state of the logic signal generated by said EPROM device.

13. An integrated circuit device comprising:

electronic logic circuit means responsive to at least one control signal and operable to perform a particular logic function on at least one input data signal to generate at least one commensurate output signal; and

programmable control means for causing said logic circuit means to have particular circuit configurations, and including;

a first reprogrammable memory device which may be programed to generate either a logic signal of a first state or a logic signal of a second state;

a first programming means connected to said first reprogrammable memory device and responsive to input program data signals and a corresponding address signal and operative to program said first reprogrammable memory device by applying a programming potential thereto;

a first sense means connected to said first reprogrammable memory device for sensing the state of the logic signal generated by said first reprogrammable memory device and for developing a commensurate first control signal for controlling said logic circuit means.

14. An integrated circuit device as recited in claim 13 wherein said electronic logic circuit means includes an exclusive NOR gate.

15. An integrated circuit device as recited in claim 14 wherein said first memory device is an EPROM transistor.

16. An integrated circuit device as recited in claim 14 wherein said first memory device is an EEPROM transistor.

17. An integrated circuit device as recited in claim 13 wherein said programmable means further includes

a second reprogrammable memory device which may be programmed to generate either a logic signal of a first state or a logic signal of a second state;

a second programming means connected to said second reprogrammable memory device and responsive to input program data signals and a corresponding address signal and operative to program said second reprogrammable memory device by applying a programming potential thereto;

a second sense means connected to said second reprogrammable memory device for sensing the state of the logic signal generated by said second reprogrammable memory device and for developing a commensurate second control signal for controlling said logic circuit means;

and wherein said logic circuit means includes

a first AND gate having a first input for receiving a first input data signal, and a second input for receiving said first control signal and operative to generate a first intermediate data signal;

at least a second AND gate having a first input for receiving a second input data signal, and a second input for receiving said second control signal and operative to generate a second intermediate data signal; and

an OR gate responsive to said first and second intermediate data signals and operative to generate said output signal.

18. An integrated circuit device as rectied in claim 17 wherein said first and second reprogrammable memory devices are EPROM transistors.

19. An integrated circuit device as recited in claim 17 wherein said first and second reprogrammable memory devices are EEPROM transistors.