Digital memory system

• US 4,713,794 A
• Filed: 02/22/1982
• Issued: 12/15/1987
• Est. Priority Date: 12/22/1978
• Status: Expired due to Fees

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Pease, William M., Byington, Roy E.
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US06/350,932
• Time in Patent Office: 2,122 Days
• Field of Search: 365/45, 364/602
• US Class Current: 365/45
• CPC Class Codes: G01R 13/345 for displaying sampled signals by using digital processors by intermediate A.D. and D.A. convertors (control circuits for CRT indicators)
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence

Abstract

A digital memory system is described wherein a plurality of digital storage sections are simultaneously fed by an analog signal. Each storage section is adapted to store a sample of such analog signal in response to a pulse. Trains of pulses are fed to the storage sections, the pulses in each train being displaced in time from a succeeding train an amount T/n where n is the number of storage sections and T is related to the bandwidth of the analog signal.

Claims

1. A method for storing digital samples representative of the level of an analog signal comprising the step of feeding the analog signal directly into a digital memory.

2. The method recited in claim 1 wherein the digital memory is a digital shift register and wherein the feeding step comprises feeding the analog signal directly into the digital shift register.

3. A method comprising the steps of:

(a) feeding an analog signal directly into a digital shift register;

(b) feeding a train of clock pulses to the shift register; and

(c) storing a logical signal in the shift register in response to each one of the clock pulses in the train thereof, each stored logical signal having a logical state related to the level of the analog signal at the time said one of the clock pulses is fed to the shift register.

4. A method for storing a series of logical signals in a digital shift register, each one of said logical signals being related to the level of an analog signal at a sampling time comprising the steps of:

(a) feeding the analog signal directly into the shift register;

(b) feeding a clock pulse to the shift register at each sampling time; and

(c) storing one of the series of logical signals in the digital shift register in response to said clock pulse.

5. A method of storing a digital sample of the level of an analog signal characterized in that the analog signal is fed to a digital memory without any intervening analog-to-digital conversion of said analog signal.

6. A method comprising the steps of:

(a) feeding an analog signal into a digital shift register;

(b) feeding a train of clock pulses to the shift register; and

(c) storing a logical signal in the shift register without any intervening analog-to-digital conversion of the analog signal in response to each one of the clock pulses in the train thereof, each stored logical signal having a logical state related to the level of the analog signal at the time said one of the clock pulses is fed to the shift register.

7. A method for storing a digital sample of an analog signal comprising the steps of:

(a) feeding the analog signal to a digital memory without any analog-to-digital conversion of the analog signal;

(b) feeding a stored enable signal to the digital memory; and

(c) storing a digital signal in the digital memory representative of the amplitude of the analog signal at the time the stored enable signal is fed to the digital memory.

8. The method recited in claim 7 wherein the digital memory is a digital shift register.

9. A method comprising the steps of:

(a) feeding an analog signal having a time varying level to a digital shift register without any intervening analog-to-digital conversion of such analog signal;

(b) feeding a drain of pulses to the digital shift register, and

(c) storing a logical signal in the digital shift register in response to each one of the pulses in the train of pulses, each one of the stored logical signals having a logical state relative to the level of the analog signal at the time said one of the pulses is fed to the digital shift register.