Apparatus and method for effecting dynamic address translation in a microprocessor implemented data processing system

• US 4,714,993 A
• Filed: 09/26/1986
• Issued: 12/22/1987
• Est. Priority Date: 10/18/1983
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Sucher, Daniel J., Walk, Bruce M., Livingston, David L.
• Primary Examiner(s): Harkcom, Gary V.
• Assistant Examiner(s): CLARK, DAVID
• Application Number:
  US06/912,165
• Time in Patent Office: 452 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/206
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures

Abstract

The performance of a multi-microprocessor implemented data processing system that emulates a mainframe system is enhanced and optimized in view of space and power constraints for purposes of address translation by providing RAM-based storage means of predetermined depth and width to function as a page address table. The storage means depth is set to at least provide bit space to represent the total number of fixed size pages possible in a given virtual memory space. The width of the storage means is set to at least provide bit space to represent the largest page number that might be encountered in the available real memory and to accommodate a predetermined number of bits that flag information pertinent to translation and system performance. Circuit means, including microcode, is provided for initializing and updating the contents of the storage means as required. Further, when the translation capability is off, a real out-of-bounds flag bit in the storage means can be used to dynamically insure that a real out-of-bounds condition is not produced. The storage means is coupled to the microprocessor address bus from when it receives the page portion of a virtual address for which a real address is desired.

Claims

1. A dual purpose apparatus capable of operating in translation mode and segmentation mode for effecting virtual to real address translations using fixed page sizes in a microprocessor implemented data processing system having predetermined real storage and virtual storage while in said translation mode, and for effecting real storage segmentation while in said segmentation mode, comprising:

a microprocessor address bus;

table storage means connected to said address bus for storing a plurality of dual purpose pages, said storage means capable of storing the total number of pages possible in said predetermined virtual storage, each of said pages further comprising;

a translation information field; and

a real out-of-bounds bit;

accessing means, connected to said storage means, for accessing only said translation information field when said apparatus is in said translation mode and for accessing only said real out of bounds bit when said apparatus is in said segmentation mode.

2. The dual purpose apparatus according to claim 1, further comprising:

mode selection means for selecting a mode of operation of said dual purpose apparatus, said selection means capable of selecting translation mode and segmentation mode.

3. The dual purpose apparatus according to claim 1, wherein said accessing means further comprises:

modification means for modifying said real out of bounds bit, thereby changing the segmentation of said real storage.

4. The dual purpose apparatus according to claim 1, wherein said translation information field further comprises:

a real address field and a page fault bit.

5. The dual purpose apparatus according to claim 1, further comprising:

a multiplexing means having a first input, a second input, and an output, said second input connected to said microprocessor address bus, said first input connected to said table storage means, said output connected to said real storage, said multiplexing means for multiplexing said first input to said output when said dual purpose apparatus is in said translation mode, and for multiplexing said second input to said output when said dual purpose apparatus is in said segmentation mode.

6. A dual purpose apparatus capable of operating in translation mode and segmentation mode for effecting virtual to real address translations using fixed page sizes in a microprocessor implemented data processing system having predetermined real storage and virtual storage while in said translation mode, and for effecting real storage segmentation while in said segmentation mode, comprising:

a microprocessor address bus;

a page address table having an input and output of predetermined bit width and connected to said microprocessor address bus at said input, said table having a depth at least equal to the total number of pages possible in said predetermined virtual storage and a width at least equal to the number of bits needed to represent the largest real page address that can be encountered in said predetermined real storage plus a plurality of flag bits wherein one of said flag bits is a real-out-of-bounds bit;

control means connected to said page address table for initializing said page address table, including means for updating a portion of the contents thereof, and means for reading a portion of the contents thereof;

mode selection means for selecting a mode of operation of said dual purpose apparatus, said selection means capable of selecting translation mode and segmentation mode;

a mode selection register means for holding an indication therein of the mode selected by said mode selection means; and

a multiplexer circuit having an untranslated data input, a translated data input, a control line input, and an multiplexer output, said untranslated data input connected to said microprocessor address bus, said translated data input connected to said page address table, said multiplexer output connected to said real storage, and said control line input connected to said mode selection holding means to responsively select said untranslated data input to be switched to said multiplexer output when said mode selection means has selected said segmentation mode, and to responsively select said translated data input to be switched to said multiplexor output when said mode selection means has selected said translation mode,

wherein each real-out-of-bounds bit associated with each page of said page address table is individually programmable by said control means so that said real storage can be programmably segmented,

wherein said real out of bounds bit is ignored when said dual purpose apparatus is in said translation mode, and wherein all data occupying said width of said page address table except said real-out-of-bounds bit is ignored when said dual purpose apparatus is in said segmentation mode, thereby allowing said page address table to be used for both virtual to real address translation and for real storage segmentation.

7. A method of using a page address table comprising a plurality of dual purpose pages, said table capable of storing the total number of pages possible in a predetermined virtual storage, each of said pages comprising a real address field, a page fault bit and a real out of bounds bit, said page address table efficiently used for both virtual to real address translation and real storage segmentation, said translation comprising the steps of:

requesting a virtual page address,

requesting a data location address within said virtual page address,

selecting a page from said page table corresponding to said requested virtual page address,

checking said page fault bit to verify that said data resides in real storage,

ignoring said real out-of-bounds bit contained in said selected page,

translating said virtual page address into a real page address contained in said real address field;

said real storage segmentation comprising the steps of;

requesting a real page address,

requesting a data location address within said real page address,

selecting a page from said page table corresponding to said requested real page address,

ignoring said real address field and said page fault bit contained in said selected page, and

checking said real out of bounds bit to make sure that said requested data is within the available segment of real storage.

8. The method of claim 7 wherein said translation further comprises the steps of:

joining said real page address obtained in said translating step with said requested data location address; and

providing the requestor with the data contained in real memory at said joined address.

9. The method of claim 7 wherein said real storage segmentation further comprises the steps of:

joining said requested real address with said requested data location address; and

providing the requestor with the data contained in available segmented real memory responsive to said checking step.