Local area network bridge

• US 4,715,030 A
• Filed: 08/04/1986
• Issued: 12/22/1987
• Est. Priority Date: 08/04/1986
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Hughes, William C., Koch, Steven R., Hatfield, William T., Stein, Charles R., Shapiro, Neil R.
• Primary Examiner(s): Masinick, Michael A.
• Assistant Examiner(s): Scutch, III, Frank M.
• Application Number:
  US06/892,618
• Time in Patent Office: 505 Days
• Field of Search: 370/85, 370/88, 370/89, 340/825.5, 340/825.52
• US Class Current: 370/401
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
• CPC Class Codes: H04L 12/4625 Single bridge functionality, e.g. connection of two networks over a single bridge
• CPC Class Codes: H04L 45/745 Address table lookup; Address filtering

Abstract

Apparatus for bridging between two local area networks is disclosed. The apparatus has two bridge sides each including means for receiving or transmitting a message frame, controller means for directing an incoming message frame into a memory means shared between the bridge sides or directing a frame out of the memory means for transmission, address reading means for reading an address portion of the incoming frame and processor means for determining frame transmissibility from the address portion as provided by the address reading means. The apparatus is configured such that the processor means determines incoming frame transmissibility substantially concurrent with the controller means directing the incoming frame into the memory means.

Claims

1. Apparatus for establishing a bridge between a pair of communication networks, each of said networks being adapted to carry bit-serial message frames between devices coupled thereto, each said message frame having a leading portion including an address portion, said apparatus comprising:

a pair of bridge sides each coupled to a respective one of said networks for transmitting and receiving message frames to and from its associated communication network;

memory means, accessible by said bridge sides, for retrievably storing message frames;

each of said bridge sides including;

interface means for receiving an incoming message frame from or transmitting an outgoing message frame to its associated communication network;

processor means for determining whether said incoming message frame is transmissible from one of said networks to the other, said processor means providing a first signal upon determining said incoming message frame is transmissible;

said processor means providing a second signal effective to initiate the transmission of said outgoing message frame;

controller means for directing said incoming message frame from said interface means to said memory means, said controller means responsive to said second signal to direct said outgoing message frame from said memory means to said interface means;

means for reading and storing the address portion of said incoming message frame concurrently with said controller means directing said incoming message frame to said memory means, the stored address portion being immediately accessible by said processor means for determining the transmissibility of said incoming message frame;

said pair of bridge sides coupled together such that each of said bridge sides can function as either a receiving bridge side for receiving said incoming message frame or a transmitting bridge side for transmitting said outgoing message frame; and

upon said processor means on said receiving bridge side providing said first signal, said processor means on said transmitting bridge side responsively providing said second signal to said controller means on said transmitting bridge side;

whereby said receiving bridge side address reading means reads and stores said address portion, said receiving bridge side processor means having immediate access to said address portion to determine therefrom the transmissibility of said incoming mesage frame concurrently with said controller means directing said incoming message frame to said memory means.

2. The bridge apparatus of claim 1 wherein said memory means is a first memory means, each of said bridge sides further including:

second memory means for storing signals provided by said processor means and said controller means for retrieval by said controller means and said processor means, respectively.

3. The bridge apparatus of claim 2 and further including third memory means accessible by both said bridge sides for storing signals provided by the respective processor means on said receiving bridge side and said transmitting bridge side.

4. The bridge apparatus of claim 3 wherein each of said bridge sides maintains a table of source addresses, said table including addresses of devices coupled to the communication network associated with that bridge side, each of said bridge sides further including:

fourth memory means for storing said source address table, said fourth memory means being accessible by the processor means on the same bridge side.

5. The bridge apparatus of claim 3, each of said bridge sides further including first and second local buses, said processor means and said controller means on each said bridge side being respectively coupled to said first and second local buses;

said second memory means on each said bridge side coupled between said first and second local buses; and

said address reading means coupled to said first local bus on each said bridge side.

6. The bridge apparatus of claim 5 wherein each of said bridge sides maintains a table of source addresses, said table including addresses of devices coupled to the communication network associated with the bridge side, each of said bridge sides further including:

fourth memory means for storing said source address table, said fourth memory means being coupled to said first local bus and accessible by the processor means on the same bridge side;

said first memory means coupled between the respective second local buses of said bridge sides; and

said third memory means coupled between the respective first local buses of said bridge sides.

7. The bridge apparatus of claim 2 wherein each of said bridge sides maintains a table of source addresses, said table including addresses of devices coupled to the communication network associated with that bridge side, each of said bridge sides further including:

third memory means for storing said source address table, said third memory means being accessible by the processor means on the same bridge side.

8. The bridge apparatus of claim 7, each of said bridge sides further including first and second local buses, said processor means and said controller means on each said bridge side being respectively coupled to said first and second local buses;

said second memory means on each said bridge side coupled between said first and second local buses;

said third memory means and said address reading means coupled to said first local bus on each said bridge side; and

said first memory means coupled between the respective second local buses of said bridge sides.

9. The bridge apparatus of claim 2, each of said bridge sides further including first and second local buses, said processor means and said controller means on each said bridge side being respectively coupled to said first and second local buses;

said first memory means coupled between the respective second local buses of said bridge sides; and

said second memory means coupled between said first and second local buses on each said bridge side.

10. The bridge apparatus of claim 1 wherein said memory means is a first memory means, said bridge apparatus further including:

second memory means accessible by both said bridge sides for storing signals provided by the processor means on both said receiving bridge side and said transmitting bridge side.

11. The bridge apparatus of claim 10 wherein each of said bridge sides maintains a table of source addresses, said table including addresses of devices coupled to the communication network associated with that bridge side, each of said bridge sides further including:

third memory means for storing said source address table, said third memory means being accessible by the processor means on the same bridge side.

12. The bridge apparatus of claim 11, each of said bridge sides further including first and second local buses, said processor means and said controller means on each said bridge side being respectively coupled to said first and second local buses;

said third memory means and said address reading means coupled to said first local bus on each said bridge side;

said first memory means coupled between the respective second local buses of said bridge sides; and

said second memory means coupled between the respective first local buses of said bridge sides.

13. The bridge apparatus of claim 10, each of said bridge sides further including first and second local buses, said processor means and said controller means on each said bridge side being respectively coupled to said first and second local buses;

said first memory means coupled between the respective second local buses of said bridge sides; and

said second memory means coupled between the respective first local buses of said bridge sides.

14. The bridge apparatus of claim 1 wherein said memory means is a first memory means;

each of said bridge sides maintaining a table of source addresses, said table including addresses of devices coupled to the communication network associated with that bridge side; and

second memory means included in each said bridge side for storing said source address table, said second memory means being accessible by the processor means on the same bridge side.

15. The bridge apparatus of claim 14, each of said bridge sides further including first and second local buses, said processor means and said controller means on each said bridge side being respectively coupled to said first and second local buses;

said second memory means and said address reading means coupled to said first local bus on each said bridge side; and

said first memory means coupled between the respective second local buses on said bridge sides.

16. The bridge apparatus of claim 1, each of said bridge sides further including first and second local buses, said processor means and said controller means on each said bridge side being respectively coupled to said first and second local buses;

said address reading means coupled to said first local bus on each said bridge side; and

said memory means coupled between the respective second local buses of said bridge sides.

17. A method for bridging between a pair of communication networks, each of said networks being adapted to carry bit-serial message frames between devices coupled thereto, each of said message frames including an address portion, said bridge comprising a pair of bridge sides coupled together such that each of said bridge sides can function as either a receiving bridge side or a transmitting bridge side respectively for either receiving an incoming message frame from or transmitting an outgoing message frame to its associated network, said pair of bridge sides sharing memory means for storing a message frame, said method comprising the steps of:

receiving said incoming message frame on said receiving bridge side from the network associated therewith;

directing said incoming message frame to said memory means for storage therein;

reading said address portion of said incoming frame concurrently with said directing step;

determining on said receiving bridge side whether said incoming message frame is transmissible to the network associated with said transmitting bridge side, said determining step being performed using said address portion acquired in said reading step;

discarding said incoming message frame if it is determined to be not transmissible;

sending a signal from said receiving bridge side to said transmitting bridge side if said incoming message frame is determined to be transmissible; and

directing the transmissible incoming message frame, as said outgoing message frame, from said memory means to the communication network associated with said transmitting bridge side.

18. The method of claim 17 wherein said signal is a first signal, said method comprising the additional step of:

providing a second signal on said transmitting bridge side after said first signal is received thereby, said second signal being effective to initiate said transmissible frame directing step.

19. The method of claim 17 wherein said memory means is a first memory means, each said bridge side further including second memory means for storing a source address table including addresses of devices coupled to the communication network associated with the respective bridge side, said method comprising the additional step, following said reading step, of:

storing said address portion in said second memory means; and

said determining step further including;

determining if said address portion is included in said source address table on said receiving bridge side.

20. The method of claim 17 wherein said memory means is a first memory means, each of said bridge sides including processor means for determining the transmissibility of said incoming message frame, the processor means on said receiving bridge side providing said signal, said bridge including second memory means, shared between the processor means on the respective bridge sides, for retrievably storing signals therein, said method comprising the additional step of:

storing said signal provided by said receiving bridge side processor means in said second memory means; and

said sending step further including the processor means on said transmitting bridge side retrieving said signal from said second memory means.

21. The method of claim 20 wherein said signal is a first signal, said method including the additional step, following said signal sending step, of:

providing a second signal from said processor means on said transmitting bridge side in response to said first signal, said second signal being effective to initiate said transmissible frame directing step.

22. The method of claim 21 wherein each said bridge side further includes third memory means for storing a source address table including addresses of devices coupled to the communication network associated with the respective bridge side, said method comprising the additional step, following said reading step, of:

storing said address portion in said third memory means; and

said determining step further including;

determining if said address portion is included in said source address table on said receiving bridge side.

23. The method of claim 21 wherein each of said bridge sides further includes network interface means for transmitting the outgoing message frame to the communication network associated with the respective bridge side and controller means for directing the outgoing message frame from said first memory means to said interface means, each said bridge side additionally including third memory means, shared between the processor means and controller means on each said bridge side, for retrievably storing signals therein, said transmissible frame directing step further including the steps of:

directing said outgoing message frame from said first memory means to said network interface means on said transmitting bridge side; and

transmitting said outgoing message frame from said transmitting bridge side network interface means to the associated network;

said method including the additional step, following said second signal providing step, of;

storing said second signal in said third memory means on said transmitting bridge side for retrieval by said controller means on the last-recited bridge side.

24. The method of claim 23 wherein each said bridge side further includes fourth memory means for storing a source address table including addresses of devices coupled to the communication network associated with the respective bridge side, said method comprising the additional step, following said reading step, of:

storing said address portion in said fourth memory means; and

said determining step further including;

determining if said address portion is included in said source address table on said receiving bridge side.