Fabrication of double diffused metal oxide semiconductor transistor
First Claim
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1. A process for fabricating a double diffused metal oxide semiconductor transistor structure comprising the steps of:
- sequentially forming on a silicon substrate a thin film of gate oxide, a layer of polysilicon, and a first layer of thermally grown oxide;
etching a window through said layers and said thin film whereby said polysilicon layer is configured into gate regions having side walls and a window between said gate regions;
implanting nitrogen in said semiconductor substrate window region for forming an oxidation inhibitor to silicon;
thermally growing a second layer of silicon oxide over said side walls of said gate regions and over said window forming thereby a thin oxide pad over said window;
implanting P-type impurity material below said window;
forming silicon nitride over said second layer of thermally grown silicon oxide and patterning by masking and etching said silicon nitride to form spaced regions that define a narrow window therebetween;
implanting P+ type impurity material through said narrow window between said gate regions;
growing a localized oxide plug over said implanted P+ region by a drive-in diffusion and oxidation cycle;
implanting N-type material to form a junction adjacent to said gate region; and
opening access to said gate regions for defining metal contact regions.
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Abstract
In the fabrication process of a DMOS transistor, a window is formed between polysilicon gate regions. Nitrogen is then implanted in the window. A self-aligning oxide is deposited to cover the exposed side walls of the polysilicon gate regions. P-type impurities are implanted at the exposed surface of the window between the side walls. Using silicon nitride masking, an oxide plug is then grown in the window. N-type impurities are implanted in the window region to form a junction adjacent to the polysilicon gate regions. Metal contacts and a passivation layer are subsequently deposited by masking, and contact windows are formed to complete the transistor structure.
133 Citations
4 Claims
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1. A process for fabricating a double diffused metal oxide semiconductor transistor structure comprising the steps of:
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sequentially forming on a silicon substrate a thin film of gate oxide, a layer of polysilicon, and a first layer of thermally grown oxide; etching a window through said layers and said thin film whereby said polysilicon layer is configured into gate regions having side walls and a window between said gate regions; implanting nitrogen in said semiconductor substrate window region for forming an oxidation inhibitor to silicon; thermally growing a second layer of silicon oxide over said side walls of said gate regions and over said window forming thereby a thin oxide pad over said window; implanting P-type impurity material below said window; forming silicon nitride over said second layer of thermally grown silicon oxide and patterning by masking and etching said silicon nitride to form spaced regions that define a narrow window therebetween; implanting P+ type impurity material through said narrow window between said gate regions; growing a localized oxide plug over said implanted P+ region by a drive-in diffusion and oxidation cycle; implanting N-type material to form a junction adjacent to said gate region; and opening access to said gate regions for defining metal contact regions. - View Dependent Claims (2, 3, 4)
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Current AssigneeSiliconix Incorporated (Vishay Intertechnology Incorporated)
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Original AssigneeSiliconix Incorporated (Vishay Intertechnology Incorporated)
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InventorsCogan, Adrian I.
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Primary Examiner(s)Hearn, Brian E.
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Assistant Examiner(s)Quach, T. N.
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Application NumberUS06/871,006Time in Patent Office572 DaysField of Search29/571, 29/578, 29/576 B, 29/580, 357/23.1, 357/23.4, 148/188, 148/187, 437/24, 437/29, 437/41, 437/69US Class Current438/268CPC Class CodesH01L 21/033 comprising inorganic layersH01L 29/66712 Vertical DMOS transistors, ...
