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Integrated circuit

  • US 4,716,314 A
  • Filed: 08/06/1975
  • Issued: 12/29/1987
  • Est. Priority Date: 10/09/1974
  • Status: Expired due to Term
First Claim
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1. An integrated circuit comprising a common semiconductor body portion, said body portion comprising plural gate circuits each comprising at least one inverter transistor having emitter and base zones and at least one collector, and a complementary transistor connected to the inverter transistor for biasing same and having emitter, base and collector zones with the complementary transistor having its collector zone connected to the inverter transistor base zone, and each gate circuit having means connecting the complementary transistor base zone and the inverter transistor emitter zone in a d.c. path, said inverter transistors being arranged along substantially parallel rows with all the inverter transistor collectors of the same gate circuit being located along the same row and wherein at least some of the gate circuits occupy different lengths in the row direction, means for interconnecting inverter transistor collectors and base zones of different gate circuits located in different rows to form desired logic, said inverter transistor collector and base zone interconnecting means comprising a group of elongated signal tracks substantially all of which extend substantially their entire length in mutually parallel straight lines and over the body substantially transversely to the row directions, said signal-track-interconnected collectors in different rows being located under the interconnecting signal track, at least plural tracks in the group of signal tracks interconnecting gate circuits in non-adjacent rows and crossing over at least one gate circuit in an intervening row, a plurality of said gate circuits each having connections to said signal tracks that are spaced apart in the row direction by distances that are different from the spacings of signal track connections to other gate circuits, the biasing complementary transistor emitter zones being located along a column extending parallel to and located alongside the said group of signal tracks, and means for isolating adjacent rows of inverter transistors, wherein the body portion comprises a surface layer of first type conductivity on a substrate of second type conductivity and at the interface of the surface layer and the substrate plural buried regions of the first type conductivity are provided which are separate from each other and have a higher doping concentration than that of the surface layer, means for dividing the surface layer into plural separated islands each of which adjoins only one of the more highly doped buried regions, some of said buried regions each constituting part of a common emitter of a plurality of inverter transistors, others of said buried regions each constituting part of a common base zone for one or more complementary transistors, whereby the inverter transistor emitters of the gate circuits are separated in the semiconductor body from the associated complementary transistor base zone.

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