Integrated circuit
First Claim
1. An integrated circuit comprising a common semiconductor body portion, said body portion comprising plural gate circuits each comprising at least one inverter transistor having emitter and base zones and at least one collector, and a complementary transistor connected to the inverter transistor for biasing same and having emitter, base and collector zones with the complementary transistor having its collector zone connected to the inverter transistor base zone, and each gate circuit having means connecting the complementary transistor base zone and the inverter transistor emitter zone in a d.c. path, said inverter transistors being arranged along substantially parallel rows with all the inverter transistor collectors of the same gate circuit being located along the same row and wherein at least some of the gate circuits occupy different lengths in the row direction, means for interconnecting inverter transistor collectors and base zones of different gate circuits located in different rows to form desired logic, said inverter transistor collector and base zone interconnecting means comprising a group of elongated signal tracks substantially all of which extend substantially their entire length in mutually parallel straight lines and over the body substantially transversely to the row directions, said signal-track-interconnected collectors in different rows being located under the interconnecting signal track, at least plural tracks in the group of signal tracks interconnecting gate circuits in non-adjacent rows and crossing over at least one gate circuit in an intervening row, a plurality of said gate circuits each having connections to said signal tracks that are spaced apart in the row direction by distances that are different from the spacings of signal track connections to other gate circuits, the biasing complementary transistor emitter zones being located along a column extending parallel to and located alongside the said group of signal tracks, and means for isolating adjacent rows of inverter transistors, wherein the body portion comprises a surface layer of first type conductivity on a substrate of second type conductivity and at the interface of the surface layer and the substrate plural buried regions of the first type conductivity are provided which are separate from each other and have a higher doping concentration than that of the surface layer, means for dividing the surface layer into plural separated islands each of which adjoins only one of the more highly doped buried regions, some of said buried regions each constituting part of a common emitter of a plurality of inverter transistors, others of said buried regions each constituting part of a common base zone for one or more complementary transistors, whereby the inverter transistor emitters of the gate circuits are separated in the semiconductor body from the associated complementary transistor base zone.
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Accused Products
Abstract
A high speed I2 L circuit having a topology which is based on a layout of parallel arranged gate circuits in which the inverter transistors of each gate circuit are arranged in a row and below the signal lines to which they are connected, said signal lies extending transversely to the rows, while the complementary transistors for the current supply of the inputs of the gate circuits are situated laterally beside the signal lines. Said layout facilitates the designing of comparatively compact I2 L circuits in which various measures to increase their speed can be taken, for example, the use of dielectric isolation, reduction of the input series resistance, reversal of the doping profile and the application of a potential difference between the bases of the complementary transistors and the common emitter of the inverter transistors.
49 Citations
26 Claims
- 1. An integrated circuit comprising a common semiconductor body portion, said body portion comprising plural gate circuits each comprising at least one inverter transistor having emitter and base zones and at least one collector, and a complementary transistor connected to the inverter transistor for biasing same and having emitter, base and collector zones with the complementary transistor having its collector zone connected to the inverter transistor base zone, and each gate circuit having means connecting the complementary transistor base zone and the inverter transistor emitter zone in a d.c. path, said inverter transistors being arranged along substantially parallel rows with all the inverter transistor collectors of the same gate circuit being located along the same row and wherein at least some of the gate circuits occupy different lengths in the row direction, means for interconnecting inverter transistor collectors and base zones of different gate circuits located in different rows to form desired logic, said inverter transistor collector and base zone interconnecting means comprising a group of elongated signal tracks substantially all of which extend substantially their entire length in mutually parallel straight lines and over the body substantially transversely to the row directions, said signal-track-interconnected collectors in different rows being located under the interconnecting signal track, at least plural tracks in the group of signal tracks interconnecting gate circuits in non-adjacent rows and crossing over at least one gate circuit in an intervening row, a plurality of said gate circuits each having connections to said signal tracks that are spaced apart in the row direction by distances that are different from the spacings of signal track connections to other gate circuits, the biasing complementary transistor emitter zones being located along a column extending parallel to and located alongside the said group of signal tracks, and means for isolating adjacent rows of inverter transistors, wherein the body portion comprises a surface layer of first type conductivity on a substrate of second type conductivity and at the interface of the surface layer and the substrate plural buried regions of the first type conductivity are provided which are separate from each other and have a higher doping concentration than that of the surface layer, means for dividing the surface layer into plural separated islands each of which adjoins only one of the more highly doped buried regions, some of said buried regions each constituting part of a common emitter of a plurality of inverter transistors, others of said buried regions each constituting part of a common base zone for one or more complementary transistors, whereby the inverter transistor emitters of the gate circuits are separated in the semiconductor body from the associated complementary transistor base zone.
- 11. An integrated circuit comprising a common semiconductor body portion, said body portion comprising plural gate circuits each comprising at least one inverter transistor having emitter and base zones and at least one collector and a complementary transistor connected to the inverter transistor for biasing same and having emitter, base and collector zones, a group of signal tracks on the body, means for connecting inverter transistor collectors of different gate circuits to the signal tracks to form desired logic, means for connecting the complementary transistor collector to the base zone of the inverter transistor it is to bias, and impedance means including a Schottky diode coupled between the complementary transistor base zone and the inverter transistor emitter for establishing a small potential difference therebetween.
- 13. An integrated circuit comprising a common semiconductor body portion, said body portion comprising plural gate circuits each comprising at least one inverter transistor having emitter and base zones and at least one collector and a complementary transistor connected to the inverter transistor for biasing same and having emitter, base and collector zones with the complementary transistor collector zone conected to the inverter transistor base zone and each gate circuit having means connecting the complementary transistor base zone and the inverter transistor emitter zone in a d.c. path, said inverter transistors being arranged along substantially parallel rows with all the inverter transistor collectors of the same gate circuit being located along the same row, a group of substantially straight and substantially parallel signal tracks on the body and extending substantially transversely to the row directions, means for connecting inverter transistor collectors of different gate circuits located in different rows to the signal tracks to form desired logic, said signal-track-interconnected collectors in different rows being located under the interconnecting signal track, the biasing complementary transistors being located alongside the said group of signal tracks, means for isolating adjacent rows of inverter transistors, said body portion comprising a surface layer of a first type conductivity and of given conductivity on a substrate having at least one region of first type conductivity but of higher conductivity than the given conductivity, the inverter transistor base zones being second type locally overdoped zones located above and adjoining said higher conductivity one region, the second type doping profile in the inverter transistor base zones decreasing from the said one region towards the surface of the surface layer, and the inverter transistor base zones having active parts present between the inverter transistor emitter and collector and adjoining inactive parts which extend up to the surface and which comprise a more highly doped region, the volume integral of the impurity doping per surface unit of the inverter transistor base zone being smaller for the active part than for the inactive part.
- 16. An integrated circuit comprising a common semiconductor body portion, said body portion comprising plural gate circuits each comprising at least one inverter transistor having emitter and base zones and at least one collector and a complementary transistor connected to the inverter transistor for biasing same and having emitter, base and collector zones with the complementary transistor collector zone connected to the inverter transistor base zone and each gate circuit having means connecting the complementary transistor base zone and the inverter transistor emitter zone in a d.c. path, said inverter transistors being arranged along substantially parallel rows with all the inverter transistor collectors of the same gate circuit being located along the same row, a group of substantially straight and substantially parallel signal tracks on the body and extending substantially transversely to the row directions, means for connecting inverter transistor collectors of different gate circuits located in different rows to the signal tracks to form desired logic, said signal-track-interconnected collectors in different rows being located under the interconnecting signal track, the biasing complementary transistors being located alongside the said group of signal tracks, means for isolating adjacent rows of inverter transistors, and means to reduce the input series resistance of the gate circuits, said series resistance reducing means including said inverter transistors of a gate circuit present in a row having a common comb-shaped base zone, the ridge of the comb extending in the direction of the rows and the teeth of the comb which extend transversely to the ridge comprising the collectors of the inverter transistors.
- 18. An integrated circuit comprising a common semiconductor body portion, said body portion comprising plural gate circuits each comprising at least one inverter transistor having emitter and base zones and at least one collector and a complementary transistor connected to the inverter transistor for biasing same and having emitter, base and collector zones with the complementary transistor collector zone connected to the inverter transistor base zone and each gate circuit having means connecting the complementary transistor base zone and the inverter transistor emitter zone in a d.c. path, said inverter transistors being arranged along substantially parallel rows with all the inverter transistor collectors of the same gate circuit being located along the same row, a group of substantially straight and substantially parallel signal tracks on the body and extending substantially transversely to the row directions, means for connecting inverter transistor collectors of different gate circuits located in different rows to the signal tracks to form desired logic, said signal-track-interconnected collectors in different rows being located under the interconnecting signal track, the biasing complementary transistors being located alongside the said group of signal tracks, means for isolating adjacent rows of inverter transistors, and means to reduce the input series resistance of the gate circuits, said series resistance reducing means including said gate circuits being constructed in the form of a comb having a ridge and teeth with the inverter transistor base zones arranged as the teeth of the comb transversely to the ridge, the ridge comprising a strip-shaped conductor track on the body contacting the inverter transistor base zones and being connected to the associated collector zones of the biasing complementary transistor.
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22. An integrated circuit comprising a common semiconductor body portion, said body portion comprising plural gate circuits each comprising at least one inverter transistor having emitter and base zones and at least one collector, and a complementary transistor connected to the inverter transistor for biasing same and having emitter, base and collector zones with the complementary transistor having its collector zone connected to the inverter transistor base zone, and each gate circuit having means connecting the complementary transistor base zone and the inverter transistor emitter zone in a d.c. path, said inverter transistors being arranged along substantially parallel rows with all the inverter transistor collectors of the same gate circuit being located along the same row and wherein at least some of the gate circuits occupy different lengths in the row direction, means for interconnecting inverter transistor collectors and base zones of different gate circuits located in different rows to form desired logic, said inverter transistor collector and base zone interconnecting means comprising a group of elongated signal tracks substantially all of which extend substantially their entire length in mutually parallel straight lines and over the body substantially transversely to the row directions, said signal-track-interconnected collectors in different rows being located under the interconnecting signal track, at least plural tracks in the group of signal tracks interconnecting gate circuits in non-adjacent rows and crossing over at least one gate circuit in an intervening row, a plurality of said gate circuits each having connections to said signal tracks that are spaced apart in the row direction by distances that are different from the spacings of signal track connections to other gate circuits, the biasing complementary transistor emitter zones being located along a column extending parallel to and located alongside the said group of signal tracks, and means for isolating adjacent rows of inverter transistors, wherein the body comprises a surface layer of a first type conductivity and of given conductivity on a substrate having at least one region of first type conductivity but of higher conductivity than the given conductivity, the inverter transistor base zones being second type locally overdoped zones located above and adjoining said higher conductivity one region and the second type doping profile in the inverter transistor base zones decreases from the said one region towards the surface of the surface layer.
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23. An integrated circuit comprising a common semiconductor body portion, said body portion comprising plural logic gate circuits each comprising at least one inverter transistor having emitter and base zones and at least one collector and a complementary transistor connected to the inverter transistor for biasing same and having emitter, base and collector zones with the complementary transistor collector zone connected to the inverter transistor base zone and each gate circuit having means connecting the complementary transistor base zone and the inverter transistor emitter zone in a d.c. path, said inverter transistors being arranged along substantially parallel rows which are divided into groups each comprising at least two rows with all the inverter transistor collectors of the same gate circuit being located along the same row, a group of substantially straight and substantially parallel signal tracks on the body and extending substantially transversely to the row directions, means for connecting inverter transistor collectors of different gate circuits located in different rows to the signal tracks to form desired logic, said signal-track-interconnected collectors in different rows being located under the interconnecting signal track, the biasing complementary transistors being located alongside said group of signal tracks, the inverter transistor emitter zones being of a first type conductivity, the inverter base zones being of a second, opposite type conductivity, dielectric isolation means extending from the surface into the body between the base zones of the inverter transistors for isolating adjacent rows of inverter transistors, said body portion comprising a surface layer of a first type conductivity at whose surface is provided a connection for the emitter zones of the inverter transistors, a plurality of strip-shaped surface regions of the first type conductivity each forming a portion of said surface layer and having a thickness extending from the surface at least partly into the layer and a width extending laterally between adjacent ones of said rows and a length extending in the direction of the rows, the inverter transistor emitter zones of said adjacent rows extending to and being in direct contact with the strip-shaped surface region situated therebetween, said dielectric isolation means including a portion extending from the surface into the body and laterally separating each strip-shaped region from the adjacent rows of inverter transistors.
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24. An integrated circuit comprising a common semiconductor body portion, said body portion comprising plural gate circuits each comprising at least one inverter transistor having emitter and base zones and at least one collector, and a complementary transistor connected to the inverter transistor for biasing same and having emitter, base and collector zones with the complementary transistor having its collector zone connected to the inverter transistor base zone, and each gate circuit having means connecting the complementary transistor base zone and the inverter transistor emitter zone in a d.c. path, said inverter transistor being arranged along substantially parallel rows with all the inverter transistor collectors of the same gate circuit being located along the same row and wherein at least some of the gate circuits occupy different lengths in the row direction means for interconnecting inverter transistor collectors and base zones of different gate circuits located in different rows to form desired logic, said inverter transistor collector and base zone interconnecting means comprising a group of elongated signal tracks substantially all of which extend substantially their entire length in mutually parallel straight lines and over the body substantially transversely to the row directions, said signal-track-interconnected collectors in different rows being located under the interconnecting signal track, at least plural tracks in the group of signal tracks interconnecting gate circuits in nonadjacent rows and crossing over at least one gate circuit in an intervening row, a plurality of said gate circuits each having connections to said signal tracks that are spaced apart in the row direction by distances that are different from the spacings of signal track connections to other gate circuits, the biasing complementary transistor emitter zones being located along a column extending parallel to and located alongside the said group of signal tracks, means for isolating adjacent rows of inverter transistors, said body portion comprising a surface layer of first type conductivity on a substrate of second type conductivity and at the interface of the surface layer and the substrate plural buried regions of the first type conductivity are provided which are separate from each other and have a higher doping concentration than that of the surface layer, means for dividing the surface layer into plural separated islands each of which adjoins only one of the more highly doped buried regions, some of said buried regions each constituting part of a common emitter of a plurality of inverter transistors, others of said buried regions each constituting part of a common base zone for one or more complementary transistors, whereby the inverter transistor emitters of the gate circuits are separated in the semiconductor body from the associated complementary transistor base zone, and means including a Schottky diode in or on said semiconductor body for applying a potential difference between at least one of the common emitters of the inverter transistors and the base zone of the associated complementary transistor.
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25. An integrated circuit comprising a common semiconductor body portion, said body portion comprising plural gate circuits each comprising at least one inverter transistor having emitter and base zones and at least one collector, and a complementary transistor connected to the inverter transistor for biasing same and having emitter, base and collector zones with the complementary transistor having its collector zone connected to the inverter transistor base zone, and each gate circuit having means connecting the complementary transistor base zone and the inverter transistor emitter zone in a d.c. path, said inverter transistors being arranged along substantially parallel rows with all the inverter transistor collectors of the same gate circuit being located along the same row and wherein at least some of the gate circuits occupy different lengths in the row direction, means for interconnecting inverter transistor collectors and base zones of different gate circuits located in different rows to form desired logic, said inverter transistor collector and base zone interconnecting means comprising a group of elongated signal tracks substantially all of which extend substantially their entire length in mutually parallel straight lines and over the body substantially transversely to the row directions, said signal-track-interconnected collectors in different rows being located under the interconnecting signal track, at least plural tracks in the group of signal tracks interconnecting gate circuits in nonadjacent rows and crossing over at least one gate circuit in an intervening row, a plurality of said gate circuits each having connections to said signal tracks that are spaced apart in the row direction by distances that are different from the spacings of signal track connections to other gate circuits, the biasing complementary transistor emitter zones being located along a column extending parallel to and located alongside the said group of signal tracks, means for isolating adjacent rows of inverter transistors, said body portion comprising a surface layer of first type conductivity on a substrate of second type conductivity and at the interface of the surface layer and the substrate plural buried regions of the first type conductivity are provided which are separate from each other and have a higher doping concentration than that of the surface layer, means for dividing the surface layer into plural separated islands each of which adjoins only one of the more highly doped buried regions, some of said buried regions each constituting a part of a common emitter of a plurality of inverter transistors, others of said buried regions each constituting part of a common base zone for one or more complementary transistors, whereby the inverter transistor emitters of the gate circuits are separated in the semiconductor body from the associated complementary transistor base zone, at least some of the complementary transistors being arranged in plural groups in which they have their base zones connected together and further including an impedance element coupling said base zones of each group to the common emitter of the associated inverter transistors for applying a potential difference therebetween.
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26. An integrated circuit comprising a common semiconductor body portion, said body portion comprising plural gate circuits each comprising at least one inverter transistor having emitter and base zones and at least one collector lying above said base zone and a complementary transistor connected to the inverter transistor for biasing same and having emitter, base and collector zones with the complementary transistor having its collector zone connected to the inverter transistor base zone, and each gate circuit having means connecting the complementary transistor base zone and the inverter transistor emitter zone in a d.c. path, said inverter transistors being arranged along substantially parallel rows with all the inverter transistor collectors of the same gate circuit being located along the same row and wherein at least some of the gate circuits occupy different lengths in the row direction, means for interconnecting inverter transistor collectors and base zones of different gate circuits located in different rows to form desired logic, said inverter transistor collector and base zone interconnecting means comprising a group of elongated signal tracks substantially all of which extend substantially their entire length in mutually parallel straight lines and over the body substantially transversely to the row directions, said signal-track-interconnected collectors in different rows being located under the interconnecting signal track, at least plural tracks in the group of signal tracks interconnecting gate circuits in nonadjacent rows and crossing over at least one gate circuit in an intervening row, a plurality of said gate circuits each having connections to said signal tracks that are spaced apart in the row direction by distances that are different from the spacings of signal track connections to other gate circuits, the biasing complementary transistor emitter zones being located along a column extending parallel to and located alongside the said group of signal tracks, means for isolating adjacent rows of inverter transistors, and means for reducing the input series resistance of the gate circuits, said last-mentioned means comprising a more highly doped body portion in and extending substantially the full length of each of a plurality of the inverter transistor base zones, the parts of the inverter transistor base zone located directly under each inverter transistor collector being spaced from said more highly doped body portion of the inverter transistor base zone.
Specification