Multiple output allpass switched capacitor filters

• US 4,716,388 A
• Filed: 12/24/1984
• Issued: 12/29/1987
• Est. Priority Date: 12/24/1984
• Status: Expired due to Fees

• Current Assignee: Gordon M. Jacobs
• Original Assignee: Gordon M. Jacobs
• Inventors: Jacobs, Gordon M.
• Primary Examiner(s): Nussbaum, Marvin L.
• Application Number:
  US06/685,319
• Time in Patent Office: 1,100 Days
• Field of Search: 333/173, 333/167, 333/172, 364/724, 364/725, 364/825, 328/151, 328/167, 330/9, 330/109, 330/110
• US Class Current: 333/173
• CPC Class Codes: H03H 19/002 N-path filters

Abstract

This invention comprises two separate topologies for implementing a second order allpass function filter which is vital for equalization of the phase of other arbitrary response magnitude shaping filters. While the allpass response itself does not affect the frequency spectrum of the signal, these topologies have available outputs that have either bandpass or bandstop characteristics. Thus, two types of useful frequency characteristics formed by the filters that have exactly the same resonant frequency and Q (or Quality factor). Using the well known general two amplifier topology to implement a monolithic switched allpass filter with a high Q leads to very high capacitance ratios and hence excessive silicon area in manufacture. Both the topologies described here reduce the required silicon area by either reducing the required capacitance ratios or making the sensitivity to the smallest capacitor extremely small allowing it to violate otherwise necessary area-to-perimeter matching of the capacitor geometries. Reducing the overall silicon area reduces the overall cost of producing the filters and allows more functionality to be integrated on a single silicon chip.

Claims

1. A multiple output allpass biquadratic filter comprising:

a biquadratic filter section having an input port and an output port and exhibiting either a bandpass or bandstop frequency response characteristic at said output port when a signal is applied to said input port;

a two input summation circuit whose output port produces the sum of the signals present at its two input ports according to the equation

space="preserve" listing-type="equation">V.sub.out =aV.sub.1 +bV.sub.2

where V_out is the signal at the summation circuit output port, V₁ is the signal at the summation circuit first input port, V₂ is the signal at the summation circuit second input port, and both the constants a and b can be positive or negative but not equal to zero;

a signal input terminal connected to both the input port of said biquadratic filter section and the first input port of said summation circuit;

a connection between the output port of the biquadtradic filter section and the second input port of said summation circuit;

a primary output terminal having an allpass frequency response characteristic that is the output port of the addition circuit;

a secondary output terminal that is the output port of the biquadratic filter section.

2. A multiple output switched capacitor filter comprising:

first and second operational amplifiers (55,60), each having an inverting input port (65,67), a non-inverting input port (66,68), and an output port (56,64);

a capacitor (53) connected between the output port (56) of the first amplifier (55) and the inverting input port (65) of the first amplifer;

a capacitor (61) connected between the output port (64) of the second amplifier (60) and the inverting input port (67) of the second amplifier;

a connection between the non-inverting input ports (66,68) of the first and second amplifiers (55,60) and the circuit signal reference node herein referred to as "ground";

a non-inverting switched capacitor connected between the output port (64) of the second amplifier (60) and the inverting input port (65) of the first amplifier (55), said switched capacitor including

a capacitor (54) having a first and second plate;

first switch means for connecting said first plate of said capacitor (54) to said output port (64) of the second amplifier (60) during phase one of a continuous non-overlapping two phase clock generator;

second switch means for connecting said first plate of said capacitor (54) to ground during phase two of said clock generator;

third switch meand for connecting said second plate of said capacitor (54) to ground during phase one of said clock generator;

fourth switch means for connecting said second plate of said capacitor (54) to said input port (65) of the first amplifier (55) during phase two of said clock generator;

an inverting switched capacitor connected between the output port (56) of the first amplifier (55) and the inverting input port (67) of the second amplifier (60), said switched capacitor including

a capacitor (59) having a first and second plate;

fifth switch means for connecting said first plate of said capacitor (59) to ground during phase one of said clock generator;

sixth switch means for connecting said first plate of said capacitor (59) to said output port (56) of the first amplifier (55) during phase two of said clock generator;

seventh switch means for connecting said second plate of said capacitor (59) to ground during phase one of said clock generator;

eighth switch means for connecting said second plate of said capacitor (59) to said input port (67) of the second amplifier (60) during phase two of said clock generator;

a capacitor (58) connected between the output port (56) of the first amplifier (55) and the inverting input port (67) of the second amplifier (60);

a capacitor (52) connected between a signal input terminal (51) and the inverting input port (65) of the first amplifier (55);

a capacitor (71) connected between a signal input terminal (51) and the inverting input port (67) of the second amplifier (60);

a two input summation circuit (57) whose output port (63) produces the sum of the signals present at its two input ports according to the equation

space="preserve" listing-type="equation">V.sub.out =aV.sub.1 +bV.sub.2

where V_out is the signal at the summation circuit output port, V₁ is the signal at the summation circuit first input port, V₂ is the signal at the summation circuit second input port, and both the constants a and b can be positive or negative but not equal to zero;

a connection between the input terminal (51) and the first input port of said summation circuit (57);

a connection between the output port (56) of the first amplifier (55) and the second input port of said summation circuit (57);

a primary output terminal that is the output port (63) of the summation circuit (57);

a secondary output terminal that is the output port (56) of the first amplifier (55).

3. The filter in accordance with claim 2 wherein all of said capacitors, switched capacitors, and the constant factors a and b of said summation circuit have pre-selected values in related ratios to each other in order to provide a filter with pre-determined characteristics at each of its primary and secondary output terminals.

4. The filter in accordance with claim 2 wherein all of said switch means are MOS transistors and all of said capacitors, switched capacitors, and the constant factors a and b of said summation circuit have pre-selected values in related ratios to each other in order to provide a filter with pre-determined allpass characteristics at its primary output terminal (63) and bandpass characteristics at its secondary output terminal (56) where the pole frequency and Q of the bandpass filter characteristics are identical to that of the allpass characteristics.

5. A multiple output switched capacitor filter comprising:

first and second operational amplifiers (35,40), each having an inverting input port (45,47), a non-inverting input port (46,48), and an output port (36,44);

a capacitor (33) connected between the output port (36) of the first amplifier (35) and the inverting input port (45) of the first amplifier;

a capacitor (41) connected between the output port (44) of the second amplifier (40) and the inverting input port (47) of the second amplifier;

a connection between the non-inverting input ports (46,48) of the first and second amplifiers (35,40) and the circuit signal reference node herein referred to as "ground";

a non-inverting switched capacitor connected between the output port (44) of the second amplifier (40) and the inverting input port (45) of the first amplifier (35), said switched capacitor including

a capacitor (34) having a first and second plate;

first switch means for connecting said first plate of said capacitor (34) to said output port (44) of the second amplifier (40) during phase one of a continuous non-overlapping two phase clock generator;

second switch means for connecting said first plate of said capacitor (34) to ground during phase two of said clock generator;

third switch means for connecting said second plate of said capacitor (34) to ground during phase one of said clock generator;

fourth switch means for connecting said second plate of said capacitor (34) to said input port (45) of the first amplifier (35) during phase two of said clock generator;

an inverting switched capacitor connected between the output port (36) of the first amplifier (35) and the inverting input port (47) of the second amplifier (40), said switched capacitor including

a capacitor (39) having a first and second plate;

fifth switch means for connecting said first plate of said capacitor (39) to ground during phase one of said clock generator;

sixth switch means for connecting said first plate of said capacitor (39) to said output port (36) of the first amplifier (35) during phase two of said clock generator;

seventh switch means for connecting said second plate of said capacitor (39) to ground during phase one of said clock generator;

eighth switch means for connecting said second plate of said capacitor (39) to said input port (47) of the second amplifier (40) during phase two of said clock generator;

a capacitor (38) connected between the output port (36) of the first amplifier (35) and the inverting input port (47) of the second amplifier (40);

a capacitor (32) connected between a signal input terminal (31) and the inverting input port (45) of the first amplifier (35);

an inverting switched capacitor connected between the signal input terminal (31) and the inverting input port (47) of the second amplifier (40), said switched capacitor including

a capacitor (42) having a first and second plate;

ninth switch means for connecting said first plate of said capacitor (42) to ground during phase one of said clock generator;

tenth switch means for connecting said first plate of said capacitor (42) to said signal input terminal (31) during phase two of said clock generator;

eleventh switch means for connecting said second plate of said capacitor (42) to ground during phase one of said clock generator, said eleventh switch means being connected between the same circuit nodes as said seventh switch means and therefore optionally combined with said seventh switch means into a single switch means;

twelfth switch means for connecting said second plate of said capacitor (42) to said input port (47) of the second amplifier (40) during phase two of said clock generator said twelfth switch means being connected between the same circuit nodes as said eighth switch means and therefore optionally combined with said eighth switch means into a single switch means;

a two input summation circuit (37) whose output port (43) produces the sum of the signals present at its two input ports according to the equation

space="preserve" listing-type="equation">V.sub.out =aV.sub.1 +bV.sub.2

where V_out is the signal at the summation circuit output port, V₁ is the signal at the summation circuit first input port, V₂ is the signal at the summation circuit second input port, and both the constants a and b can be positive or negative but not equal to zero;

a connection between the input terminal (31) and the first input port of said sumation circuit (37);

a connection between the output port (36) of the first amplifier (35) and the second input port of said summation circuit (37);

a primary output terminal that is the output port (43) of the summation circuit (37);

a secondary output terminal that is the output port (36) of the first amplifier (35).

6. The filter in accordance with claim 5 wherein all of said capacitors, switched capacitors, and the constant factors a and b of said summation circuit have pre-selected values in related ratios to each other in order to provide a filter with pre-determined characteristics at each of its primary and secondary output terminals.

7. The filter in accordance with claim 5 wherein all of said switch means are MOS transistors and all of said capacitors, switched capacitors, and the constant factors a and b of said summation circuit have pre-selected values in related ratios to each other in order to provide a filter with predetermined allpass characteristics at its primary output terminal (43) and bandstop characteristics at its secondary output terminal (36) where the pole frequency and Q of the bandstop filter characteristics are identical to that of the allpass characteristics.