Microcomputer system with buffer in peripheral storage control

• US 4,716,522 A
• Filed: 03/10/1983
• Issued: 12/29/1987
• Est. Priority Date: 03/10/1982
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Nakamura, Hideo, Iwasaki, Kazuhiko, Funabashi, Tsuneo
• Primary Examiner(s): Harkcom, Gary V.
• Assistant Examiner(s): Lacasse, Randy W.
• Application Number:
  US06/473,861
• Time in Patent Office: 1,755 Days
• Field of Search: 360/40, 360/49, 364/200 MS File, 364/900 MS File
• US Class Current: 710/56
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0656 Data buffering arrangements

Abstract

A microcomputer system has a peripheral storage control equipped with both a circuit which is responsive to a transfer command received from an MPU to set in a counter a transfer start address, which is designated subsequent to that command. The counter to supply an address for a buffer to control transfer of data from the output of the buffer to a common bus connected between the MPU and a RAM. A circuit is provided for controlling the aforementioned counter to count up in response to a transfer acknowledge signal which is subsequently received from a direct memory access control. In order that the data in the buffer may not be transferred to the RAM but may be rewritten, the peripheral storage control is further equipped with both a circuit for setting a rewrite address also received from the MPU in the counter, which is operative to identify the address of the selected buffer, in association with a rewrite command received from the MPU, and a circuit is also provided for applying the rewrite signal to the buffer each time the rewrite data is received after the setting operation from the MPU.

Claims

1. In a microcomputer system including a data processor;

a random access memory;

a common bus interconnecting said data processor and said random access memory; and

a peripheral disc storage unit in which data is stored on a disc in sectors having a predetermined number of data blocks;

a peripheral storage control for controlling data transfer between said peripheral disc storage unit and said random access memory under control of said data processor, comprising;

an internal data bus;

counter means connected to said internal data bus for storing memory addresses;

buffer means connected to said counter means for storing a sector of data read out from said peripheral disc storage unit into, and for feeding a number of data blocks which may be less than that of a sector of data to said internal data bus from, a storage location thereof having an address corresponding to that stored in said counter means;

switching means selectively connecting said buffer means to said internal data bus or said peripheral storage;

data transfer means connected between said internal data bus and said common bus and connected to receive a transfer acknowledge signal from said data processor for controlling the direction of data transfer between said internal data bus and said common bus in response to both a read/write instruction signal received on said common bus and said transfer acknowledge signal from said data processor; and

control means connected to said internal data bus and responsive to a predetermined command transferred to said internal data bus by said data transfer means for controlling said switching means, said counter means and said buffer means to effect connection between said buffer means and said peripheral disc storage unit to cause data transfer therebetween and to effect connection between said buffer means and said internal data bus to cause data transfer with said random access memory via said data transfer means and said common bus, including storing means for storing an indication of a number of blocks to be transferred and a read start address received from said data processor via said common bus and said data transfer means, means for setting said counter means with said read start address associated with said predetermined command and means for controlling said buffer means to read out a number of blocks of data, beginning at said read start address according to the data stored in said storing means.

2. A microcomputer system according to claim 1, wherein said control means comprises:

a register stack for storing a command received from said data processor via said data transfer means and said internal data bus; and

microinstruction control means connected to said counter means and said buffer means for controlling said counter means and said buffer means, and which includes means for clearing the counter means and for sending a signal to said peripheral disc storage unit to initiate transfer of data from said peripheral disc storage unit to said buffer means in response to the command transferred to said register stack from said data processor, means for presetting in the counter means a buffer address of the data to be rewritten in response to said command and said buffer address received from said data processor, and means for feeding a write signal to said buffer means so as to store data to be written which is transferred from said data processor to said buffer means via said data transfer means and said internal data bus in response to a store command of said data processor.

3. A microcomputer system according to claim 1, characterized in that said control means further comprises means for incrementing or decrementing said counter means in the operation of transferring the data between said peripheral disc storage unit and said buffer means for purposes of transferring data blocks between said data processor and said buffer means.

4. A microcomputer system according to claim 1, wherein said data processor includes a direct memory access control which transfers data between said random access memory and said buffer means on behalf of said microcomputer.

5. In a microcomputer system including a data processor;

a random access memory;

a common bus interconnecting said data processor and said random access memory; and

a peripheral disc storage unit in which data is stored on a disc in sectors having a predetermined number of data blocks;

a peripheral storage control for controlling data transfer between said peripheral disc storage unit and said random access memory under control of said data processor, comprising;

counter means for storing memory addresses;

buffer means connected to said counter means for storing a sector of data read out from said peripheral disc storage unit into, and for feeding a number of data blocks which may be less than that of a sector of data to said internal data bus from, a storage location thereof having an address corresponding to that stored in said counter means;

data transfer means connected between said buffer means and said common bus for controlling the direction of data transfer between said buffer means and said common bus in response to signals received from said data processor; and

control means connected to said data transfer means and responsive to a predetermined command from said processor means for controlling said counter means and said buffer means to effect data transfer between said buffer means and said peripheral disc storage unit and to effect data transfer between said buffer means and said data transfer means to cause data transfer with said random access memory via said data transfer means and said common bus, including storing means for storing an indication of a number of blocks to be transferred and a read start address received from said data processor via said common bus and said data transfer means, means for setting said counter means with said read start address associated with said predetermined command and means for controlling said buffer means to read out a number of blocks of data beginning at said read start address according to the data stored in said storing means.