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Bus converter

  • US 4,716,527 A
  • Filed: 12/10/1984
  • Issued: 12/29/1987
  • Est. Priority Date: 12/10/1984
  • Status: Expired due to Term
First Claim
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1. A bus converter device for compatibly interfacing a data processor having read and write operations and adapted for use with a data bus nm bytes wide with a first type of external device adapted for use with a data bus m bytes wide and a second type of external device adapted for use with a data bus nm bytes wide, said second type of external device generating a selection signal indicating that it requires a data bus nm bytes wide, said data processor including an instruction set having both m byte wide operations and nm byte wide operations, said device comprising:

  • nm bytes input data bus nm bytes wide coupled to said data processor for transmitting data between said data processor and said external devices, said input data bus being divided into low portions and high portions;

    timing and control logic means for detecting whether a data processor operation is a nm or m byte wide operation, said timing and control logic means including means for effecting a first cycle of operation when a m byte wide operation is detected and a second cycle of operation longer than said first cycle when a nm byte wide operation is detected;

    one m byte output data bus m bytes wide coupled to m byte wide external devices for transmitting data between said data processor and said m byte wide external devices;

    data bus portion selecting means coupled between said nm byte input data bus and said m byte output data bus, and responsive to said timing and control logic means for selectively coupling one of said bus portions to said m byte output data bus during a write operation and for sequentially coupling said high data bus portion to said m byte output data bus, followed by said low bus portion during a read operation; and

    means in said timing and control logic responsive to said selection signal and effective when said nm byte wide external devices are communicating with said data processor for disabling said timing and control logic means whereby said bus converter device is bypassed.

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