Semiconductor memory device with variable self-refresh cycle

• US 4,716,551 A
• Filed: 09/13/1984
• Issued: 12/29/1987
• Est. Priority Date: 09/14/1983
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Inagaki, Yasaburo
• Primary Examiner(s): Hecker, Stuart N.
• Assistant Examiner(s): GOSSAGE, GLENN
• Application Number:
  US06/650,153
• Time in Patent Office: 1,202 Days
• Field of Search: 365/222, 365/211, 365/212, 365/227, 365/109, 307/310
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles

Abstract

A semiconductor memory device with an internal refresh circuit is disclosed. The internal refresh circuit includes a timer circuit which generates a refresh request signal in a shorter cycle at a high temperature and in a longer cycle at a low temperature. The cycle of a self-refresh mode can be thereby lengthened in a low temperature to reduce a power consumption in the self-refresh mode.

Claims

1. A semiconductor memory comprising:

a plurality of address terminals;

a row address strobe terminal;

a column address strobe terminal;

a read/write control terminal;

a refresh terminal;

a memory cell array;

a first circuit coupled to said address terminals, said row address strobe terminal, said column address strobe terminal, said read/write control terminal and said memory cell array and activated during a data-read or data-write period in accordance with a level at said read/write control terminal to read data stored in a selected memory cell in said memory cell array or to write data in the selected memory cell; and

a second circuit coupled to said refresh terminal, said memory cell array and one terminal selected from said address terminals, said column address strobe terminal and said read/write control terminal and activated during a self-refresh period to refresh at least one memory cell in said memory cell array, said second circuit including an oscillator generating an oscillation signal, means for receiving a temperature detection signal supplied to said one terminal during said self-refresh period, said temperature detection signal taking a first level when an ambient temperature is equal to or higher than a predetermined value and a second level when the ambient temperature is lower than said predetermined value, and a timer circuit receiving said oscillation signal and an output of said receiving means and generating a refresh request signal in a first cycle when said temperature detection signal takes said first level and in a second cycle when said temperature detection signal takes said second level, said second circuit refreshing the memory cell in said memory cell array in response to said refresh request signal.

2. The semiconductor memory as claimed in claim 1, wherein said one terminal is said column address strobe terminal.

3. A memory device comprising:

a plurality of memory cells;

an oscillator for generating an oscillation signal;

a first capacitor;

a second capacitor;

a switch circuit provided between said first and second capacitors;

control means for controlling a state of said switch circuit;

charging means for charging said first capacitor when said switch circuit is in an off-state, and for charging both of said first and second capacitors when said switch circuit is in an on-state;

discharging means responsive to said oscillation signal for periodically discharging said first capacitor when said switch circuit is in the off-state, and for discharging both of said first and second capacitors when said switch circuit is in the on-state;

detecting means for detecting a voltage across said first capacitor; and

refresh means responsive to an output of said detecting means for refreshing at least one of said memory cells.

4. A semiconductor memory fabricated as an integrated circuit device comprising:

a plurality of memory cells formed in said integrated circuit device;

an oscillator formed in said integrated circuit device and generating a train of pulses in a predetermined frequency, said train of pulses being utilized to bias a semiconductor substrate of said integrated circuit device;

a timer circuit formed in said integrated circuit device and receiving said train of pulses;

a timer control circuit formed in said integrated circuit device and producing an operation control signal;

means formed in said integrated circuit device for supplying said operation control signal to said timer circuit,

said timer circuit operating in a first state, when said operation control signal takes a first level, to generate a refresh request signal every time a first number of said pulses are supplied thereto,

said timer circuit operating in a second state, when said operation control signal takes a second level, to generate said refresh request signal every time a second number of said pulses are supplied thereto, said first number being different from said second number, and

means formed in said integrated circuit device and responsive to said refresh request signal for refreshing said memory cells.

5. The memory as claimed in claim 4, wherein said timer control circuit produces said operation control signal in response to an ambient temperature detection signal, said operation control signal taking said first level when an ambient temperature is equal to or higher than a predetermined value and said second level when the ambient temperature is lower than said predetermined value.

6. A semiconductor memory comprising:

a plurality of memory cells;

a power supply terminal;

a reference terminal;

first and second nodes;

an oscillator for generating an oscillation signal;

a first transistor coupled between said first node and said reference terminal;

means for operatively supplying said oscillation signal to said first transistor, said first transistor producing a current path between said first node and said reference terminal in a cycle period that is determined by a cycle of said oscillation signal to decrease periodically a potential at said first node;

a first capacitor connected between said first node and said reference terminal;

means for detecting the potential at said first node to produce a refresh request signal when the potential at said first node is decreased to a predetermined level;

means responsive to said refresh request signal for refreshing at least one of said memory cells;

means for generating a refresh end signal when the refreshing of said at least one of said memory cells ends;

a second transistor connected between said power supply terminal and said first node and supplied with said refresh end signal, said second transistor producing a current path between said power supply terminal and said first node in response to said refresh end signal thereby to increase the potential at said first node to a level at said power supply terminal;

a second capacitor connected between said second node and said reference terminal;

a switch circuit connected between said first and second nodes;

means for producing a temperature detection signal, said temperature detection signal taking a first level when an ambient temperature is equal to or higher than a predetermined value and a second level when the ambient temperature is lower than said predetermined value; and

means for supplying said temperature detection signal to said switch circut, said switch circuit being turned ON when said temperature detection signal takes said first level to connect said first node to said second node and turned OFF when said temperature detection signal takes said second level to disconnect said first node from said second node.

7. The memory as claimed in claim 6, further comprising a third transistor connected between said power supply terminal and said second node, said third transistor being turned ON when said temperature detection signal takes said second level and turned OFF when said temperature detection signal takes said first level.

8. A semiconductor memory comprising:

a plurality of memory cells;

a refresh terminal is applied in a self-refresh mode;

address terminals supplied with address signals;

at least one address control terminal supplied with an address control signal;

a read/write control terminal supplied with a read/write control signal;

first means responsive to the application of said refresh signal to said refresh terminal for performing a self-refresh operation for refreshing said plurality of memory cells; and

second means responsive to said address signals, said address control signal and said read/write control signal for performing a data-read or data-write operation in accordance with a level of said read/write control signal when said refresh signal is not applied to said refresh terminal,

said first means including an oscillator generating an oscillation signal having a first cycle, a timer control circuit detecting a potential at one terminal selected from said address terminals, said at least one address control terminal and said read/write control terminal and producing a detection signal when said potential at said one terminal assumes a first logic level, a timer circuit receiving said oscillation signal and generating a refresh request signal in a second cycle when said detection signal is not produced and in a third cycle when said detection signal is produced, said first, second and third cycles being different from one another, and means responsive to said refresh request signal for refreshing said plurality of memory cells.

9. A semiconductor memory as claimed in claim 8, wherein said one terminal receives a temperature detection signal in response to which said first means performs the self-refresh operation, said temperature detection signal taking a second logic level when an ambient temperature is equal to or higher than a predetermined value and said first logic level when the ambient temperature is lower than said predetermined value, and said second cycle is shorter than said third cycle.

10. The semiconductor memory as claimed in claim 9, wherein said timer circuit includes a first capacitor connected between a circuit node and a reference potential, a second capacitor, means for connecting said second capacitor in parallel with said first capacitor when said detection signal is produced, means responsive to said oscillation signal for discharging periodically said circuit node, means for generating said refresh request signal when a potential at said circuit node is reduced to a predetermined level, and means for charging said circuit node after said refresh request signal is generated.