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Dynamic ram with capacitor groove surrounding switching transistor

  • US 4,717,942 A
  • Filed: 07/30/1984
  • Issued: 01/05/1988
  • Est. Priority Date: 07/29/1983
  • Status: Expired due to Term
First Claim
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1. A semiconductor memory device having a memory cell comprising a single insulated gate type field effect transistor and a single capacitor, said device including a semiconductor substrate of one conductivity type and having a major surface, a groove partially surrounding an area of said major surface of said substrate and extending from said major surface of said substrate towards the interior of said substrate, said groove having a bottom, a first side wall surface extending from said area of said major surface to said bottom, and a second side wall surface opposite said first side wall surface, an source or drain region of said transistor having the opposite conductivity type and formed in said major surface of said substrate, a first surface layer of said opposite conductivity type formed in said area of said major surface of said substrate and coupled to said transistor through the unsurrounded part of said area, said first surface layer having a depth less than the depth of said source or drain region of said transistor, a second surface layer of said opposite conductivity type formed along said first side wall surface of said groove and connected to said first surface layer, a first dielectric film formed on said area of said major surface, a second dielectric film formed on said first side wall surface of said groove, and a conductor layer formed on said first dielectric film above said major surface and on said second dielectric film within said groove, whereby said single capacitor of said memory cell includes a first MOS type capacitor comprising said first surface layer, said first dielectric film and said conductor layer, and a secnd MOS type capacitor comprising said second surface layer, said second dielectric film and said conductor.

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