Dynamic ram with capacitor groove surrounding switching transistor

• US 4,717,942 A
• Filed: 07/30/1984
• Issued: 01/05/1988
• Est. Priority Date: 07/29/1983
• Status: Expired due to Term

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Kuroki, Yukinori, Nakamura, Kunio
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US06/635,538
• Time in Patent Office: 1,254 Days
• Field of Search: 357/23.6, 357/23.11, 357/55, 357/50, 357/59, 365/149
• US Class Current: 257/304
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/37 the capacitor being at least partially in a trench in the substrate

Abstract

A semiconductor memory cell of a single field effect transistor and a single capacitor is surrounded or delimited at its three sides in the plan view by grooves formed in a semiconductor substrate. The capacitor in each memory cell is formed on one side wall surface or both side wall surfaces of this groove. With such construction, an increase in a capacitance can be achieved and a degree of circuit integration can be enhanced in distinction from the case where a groove is provided within an active region, that is, within a plan region of a capacitor section.

Claims

1. A semiconductor memory device having a memory cell comprising a single insulated gate type field effect transistor and a single capacitor, said device including a semiconductor substrate of one conductivity type and having a major surface, a groove partially surrounding an area of said major surface of said substrate and extending from said major surface of said substrate towards the interior of said substrate, said groove having a bottom, a first side wall surface extending from said area of said major surface to said bottom, and a second side wall surface opposite said first side wall surface, an source or drain region of said transistor having the opposite conductivity type and formed in said major surface of said substrate, a first surface layer of said opposite conductivity type formed in said area of said major surface of said substrate and coupled to said transistor through the unsurrounded part of said area, said first surface layer having a depth less than the depth of said source or drain region of said transistor, a second surface layer of said opposite conductivity type formed along said first side wall surface of said groove and connected to said first surface layer, a first dielectric film formed on said area of said major surface, a second dielectric film formed on said first side wall surface of said groove, and a conductor layer formed on said first dielectric film above said major surface and on said second dielectric film within said groove, whereby said single capacitor of said memory cell includes a first MOS type capacitor comprising said first surface layer, said first dielectric film and said conductor layer, and a secnd MOS type capacitor comprising said second surface layer, said second dielectric film and said conductor.

2. A semiconductor memory device as claimed in claim 1, further including a third dielectric film on said second side wall surface of said groove to form a MOS type capacitor of an adjacent memory cell.

3. A semiconductor memory device as claimed in claim 1 wherein first and second PN junction capacitors are formed between said first surface layer and said substrate, and between said second surface layer and said substrate, respectively.

4. A semiconductor memory device as claimed in claim 1, in which one of the source and drain regions of said transistor is connected to a digit line.

5. A semiconductor memory device as claimed in claim 1, in which an impurity region of the same conductivity type as said semiconductor substrate and having a higher impurity concentration than said semiconductor substrate, is provided in the portion of said semiconductor substrate under said bottom surface of said groove.

6. A semiconductor memory device as claimed in claim 5, said impurity region has a depth of 0.5 to 1.0 μ

m from said bottom of said groove and an impurity concentration of 5×

10¹⁸ /cm³ or higher, and the insulating film on said bottom surface of said groove has a thickness of 100 Å

or larger.

7. A semiconductor memory device comprising a semiconductor substrate of one conductivity type and having a flat major surface, first and second digit lines extending in one direction in the plan view, a first groove provided from said major surface of said substrate towards the interior of said substrate and extending in said one direction substantially along a midline between said first and second digit lines, a plurality of second grooves each provided from said major surface of said substrate towards the interior of said substrate and extending substantially at right angles to said first groove in the plan view, a plurality of surface portions of said major surface, each of said surface positions being surrounded by said first and second grooves except one side thereof, a thick field insulating film selectively formed on said substrate and at least partially embedded in said substrate such that the depth of said thick field insulating film from said flat major surface is less than that of said first and second grooves, said thick field insulating film having a plan configuration making contact with an end of each second groove, a first thin insulating film provided on the opposite side wall surfaces and the bottom surfaces of the respective ones of said first and second grooves, an impurity region of said one conductivity type and having a higher impurity concentration than said substrate provided in the portion of said substrate under said bottom surfaces of said first and second grooves, a second thin insulating film provided on each of said surface portions of said major surface, first inversion layers of the opposite conductivity type formed in said opposite side wall surfaces of at least said first groove, second inversion layers of the opposite conductivity type formed in each of said surface portions of said major surface and connected to respective said first inversion layers, a conductive layer provided on said first and second thin insulating films, insulator materials filled in respective end parts of said second grooves in proximity with the respective ends connected with said thick field insulating film, and a plurality of insulated gate type field effect transistors provided on said substrate, each of said transistors being coupled to one of said first and second bit lines and to corresponding said second inversion layer in said surface portion of said major surface, each transistor including source, drain region of the opposite conductivity type having a depth greater than that of said second inversion layer, whereby a plurality of memory cells each including one of said transistors and one capacitor coupled to said transistor are formed on said substrate, said one capacitor having a first MOS type capacitor constituted by said first inversion layer, said first insulating film and said conductive layer, and a second MOS type capacitor constituted by said second inversion layer, said second insulating film and said conductive layer.

8. A semiconductor memory device as claimed in claim 7, in which a part of PN junction capacitor in said capacitor of said memory cell is constructed of said first inversion layer of said opposite conductivity type and said semiconductor substrate in said first groove.

9. A semiconductor memory device as claimed in claim 7, in which said second grooves are entirely filled with an insulator material.

10. A semiconductor memory device as claimed in claim 7, wherein parts of said second grooves other than said end parts are filled with said conductor layer to form said first MOS type capacitor.

11. A semiconductor memory device comprising a semiconductor substrate of one conductivity type, an insulated gate type field effect transistor provided in a transistor forming area of said semiconductor substrate and having one of source and drain regions of the opposite conductivity type connected to a digit line, the other of source and drain regions of said opposite conductivity type, a channel region between said source and drain regions and a gate electrode formed on said channel region via a gate insulating film, a groove formed in said semiconductor substrate and having U shape in the plan view such that it surrounds said transistor forming area, a dielectric film formed on the both inner side wall surfaces facing each other and on the bottom surface of said groove, an impurity region of said one conductivity type having a higher impurity concentration than that of said semiconductor substrate formed in portions of said semiconductor substrate said inner side wall surfaces and the bottom surface of said groove, and a conductor layer formed on said dielectric film within said groove and connected to said the other of source and drain of said transistor, wherein said conductor layer is absent on a portion of said bottom surface of said groove, and wherein a part of said conductor layer extending on one of said inner side wall surfaces of said groove via said dielectric film serves as an upper electrode of a capacitor in a first memory cell and a part of said conductor layer extending on the other of said inner side wall surfaces of said groove via said dielectric film serves as an upper electrode of a capacitor in a second memory cell adjacent to said first memory cell, whereby a MOS capacitor of said memory cell connected to said transistor is constructed by said conductor layer connected to said other of source and drain and provided within said groove, said dielectric film and said impurity region of the same conductivity type as said substrate.