Method of data arbitration and collision detection in a data bus

• US 4,719,458 A
• Filed: 02/24/1986
• Issued: 01/12/1988
• Est. Priority Date: 02/24/1986
• Status: Expired due to Term

• Current Assignee: Continental Automotive GmbH (Continental AG)
• Original Assignee: Chrysler Corporation (Stellantis NV)
• Inventors: McCambridge, John M., Miesterfeld, Frederick O. R., Fassnacht, Ronald E.
• Primary Examiner(s): YUSKO, DONALD
• Application Number:
  US06/832,909
• Time in Patent Office: 687 Days
• Field of Search: 340/825.5, 340/825.51, 370/85, 370/94
• US Class Current: 710/240
• CPC Class Codes: F02D 41/266 the computer being backed-up or assisted by another circuit, e.g. analogue
• CPC Class Codes: G06F 13/374 using a self-select method with individual priority code comparator
• CPC Class Codes: H04L 12/4135 using bit-wise arbitration
• CPC Class Codes: H04L 2012/40273 the transportation system being a vehicle

Abstract

A method of blocking data transmission from a user microprocessor to a data bus utilizing arbitration and collision detection in a data bus interface integrated circuit utilizing a Serial Communication Interface (SCI) port on the user microprocessor.

Claims

1. In a communication system for transmission of digital messages through a data bus between two or more user microprocessors coupled to the data bus by means of a data bus interface integrated circuit, a method for blocking data transmission from the user microprocessor to the data bus when the data bus is busy comprising:

synchronizing the communication system with the occurrence of a bus idle condition;

waiting until the synchronization occurs before transmitting or receiving data messages;

if the data bus is in an idle condition, determining whether the user microprocessor has a message available to send;

attempting to win bus arbitration if a message is available to send by sending a message ID byte;

checking to see whether the message ID byte was received from the data bus;

checking to see whether the arbitration was won or lost if the message ID byte was received from the data bus, by comparing the received message ID byte to see whether it is equal to the transmitted ID byte;

sending the rest of the message if the received message ID byte is equal to the transmitted message ID byte;

determining whether any more message bytes are to be sent to the data bus and sending the next message byte if needed;

deleting the transmitted message fromthe input queue if the message is complete and returning to resynchronize with the bus idle condition;

checking to see whether the next message byte was received from the data bus if more messages need to be sent;

checking to see whether the received byte is equal to the transmitted byte and returning to check whether any more message bytes need to be sent if the received byte is equal to the transmitted byte and terminating the message transmission due to a collision if the received byte is not equal to the transmitted byte and returning to resynchronize with the bus idle condition;

checking to see whether any message ID byte is to be received if the data bus is in an idle condition;

checking to see whether the message is of interest to the user microprocessor, returning to resynchronize with the bus idle condition if it is not and saving the received byte if it is;

checking to see if there is a next byte to be received if the received byte is saved;

checking to see whether the data bus is in an idle condition and processing the received message if the data bus is in an idle condition before returning to resynchronize with the bus idle condition, but returning to look for the reception of the next byte if the bus is not in an idle condition.

2. In communication system for the transmission of messages through a data bus between one or more user microprocessors coupled to the data bus, the user microprocessors having a serial communications interface (SCI) port along with a clock port and an input/output port, the user microprocessors being coupled to the data bus by a bus interface integrated circuit, the bus interface circuit including an arbitration detector, a collision detector, a word counter, a start bit detector, a framing error detector, an idle detector, and a midbit timer, a method used by the bus interface integrated circuit, of arbitrating data from the data bus, the data having at least one start bit and at least one stop bit, with a bit-wise contention and a deterministic priority access method to (a) resolve contentions among user microprocessors that try to send messages at the same time and to (b) synchronize each data byte and to (c) allow the priority of an ID byte of the message to determine which of a plurality of messages will be sent first in the case of a contention, the determination of which user microprocessor transmits first being made without losing bus time when contention occurs;

the method comprising;

monitoring the data bus until a start bit signal is on the data bus indicating that a start bit may be on the bus;

starting a word counter, if a start bit signal is on the data bus;

monitoring the data bus to see whether a start bit level has been reached on the data bus indicating that a start bit is on the bus, if not, returning to monitor the data bus until a start bit signal is on the data bus;

monitoring the start bit detector to see if the start bit detector time is up if the start bit level is on the data bus, and returning to monitor the data bus to see whether a start bit level has been reached on the data bus if the start bit detector time is not up;

monitoring the input to the arbitration detector to see whether it is at a start bit level, setting the output of the arbitration detector equal to an idle level to indicate that the bus is idle if the signal on the input line to the arbitration detector is not at the start bit level;

if the signal on the input line to the arbitration detector is at the start bit level, monitoring the framing error detector until the stop bit time is up;

if the stop bit time is up, monitoring the data bus to see if the stop bit level is on the data bus, returning to monitor the data bus until the start bit signal is on the data bus, if the stop bit level is not on the data bus;

monitoring the idle detector until a reset signal is received from the idle detector if the stop bit level is not on the data bus, and returning to repeat the above steps if the reset signal has been received from the idle detector.

3. In communication system for the transmission of messages through a data bus between one or more user microprocessors coupled to the data bus, the user microprocessors having a serial communications interface (SCI) port along with a clock port and input/output port, the user microprocessors being coupled to the data bus by a bus interface integrated circuit, the bus interface circuit including an arbitration detector, a collision detector, a word counter, a start bit detector, a framing error detector, an idle detector, and a midbit timer, a method, used by the bus interface integrated circuit, of collision detection of data from the data bus, the data having at least one start bit and at least one stop bit, with a bit-wise contention and a deterministic priority access method to (a) resolve contentions among user microprocessors that try to send messages at the same time and to (b) synchronize each data byte and to (c) allow the priority of an ID byte of the message to determine which of a plurality of messages will be sent first in the case of a contention, the determination of which user microprocessor transmits first being made without losing bus time when contention occurs;

the method comprising;

monitoring the data bus until a start bit signal is on the data bus indicating that a start bit may be on the bus;

if the start bit signal is on the data bus, starting the word counter;

monitoring the data bus to see if the start bit level is on the data bus indicating that a start bit is on the bus, returning to monitor the data bus until a start bit signal is on the data bus if the start bit level is not on the bus;

monitoring the start bit detector to see if the start bit detector time is up if the start bit level is on the data bus, returning to monitor the data bus to see whether the start bit level is on the data bus if the start bit detector time is not up;

if the start bit detector time is up, monitoring the midbit timer in the word counter until it is up;

if the midbit timer is up, monitoring the input to the collision detector to see whether it is the same as the data on the data bus;

monitoring the framing error detector to see whether the stop bit time is up if the input to the collision detector is the same as the data on the data bus, returning to monitor the midbit timer until it is up if the stop bit time is not yet up;

monitoring the data bus to see whether the stop bit level is on the data bus if the stop bit time is up, returning to monitor the data bus until a start bit signal is on the data bus if the stop bit level is on the bus;

monitoring the idle detector until a reset signal has been received from the idle detector if the stop bit level is not on the bus;

returning to repeat the above procedure once the reset signal is received from the idle detector;

setting the output of the collision detector equal to the idle level if the input to the collision detector is not the same as the data on the data bus and thereafter monitoring the idle detector until a reset signal has been received and thereafter returning to repeat the above procedure.